1*aef65474SGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*aef65474SGeert Uytterhoeven%YAML 1.2 3*aef65474SGeert Uytterhoeven--- 4*aef65474SGeert Uytterhoeven$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml# 5*aef65474SGeert Uytterhoeven$schema: http://devicetree.org/meta-schemas/core.yaml# 6*aef65474SGeert Uytterhoeven 7*aef65474SGeert Uytterhoeventitle: Renesas EMMA Mobile EV2 System Management Unit 8*aef65474SGeert Uytterhoeven 9*aef65474SGeert Uytterhoevenmaintainers: 10*aef65474SGeert Uytterhoeven - Geert Uytterhoeven <geert+renesas@glider.be> 11*aef65474SGeert Uytterhoeven - Magnus Damm <magnus.damm@gmail.com> 12*aef65474SGeert Uytterhoeven 13*aef65474SGeert Uytterhoevendescription: | 14*aef65474SGeert Uytterhoeven The System Management Unit is described in user's manual R19UH0037EJ1000_SMU. 15*aef65474SGeert Uytterhoeven This is not a clock provider, but clocks under SMU depend on it. 16*aef65474SGeert Uytterhoeven 17*aef65474SGeert Uytterhoevenproperties: 18*aef65474SGeert Uytterhoeven compatible: 19*aef65474SGeert Uytterhoeven const: renesas,emev2-smu 20*aef65474SGeert Uytterhoeven 21*aef65474SGeert Uytterhoeven reg: 22*aef65474SGeert Uytterhoeven maxItems: 1 23*aef65474SGeert Uytterhoeven 24*aef65474SGeert Uytterhoeven '#address-cells': 25*aef65474SGeert Uytterhoeven const: 2 26*aef65474SGeert Uytterhoeven 27*aef65474SGeert Uytterhoeven '#size-cells': 28*aef65474SGeert Uytterhoeven const: 0 29*aef65474SGeert Uytterhoeven 30*aef65474SGeert Uytterhoevenrequired: 31*aef65474SGeert Uytterhoeven - compatible 32*aef65474SGeert Uytterhoeven - reg 33*aef65474SGeert Uytterhoeven - '#address-cells' 34*aef65474SGeert Uytterhoeven - '#size-cells' 35*aef65474SGeert Uytterhoeven 36*aef65474SGeert UytterhoevenpatternProperties: 37*aef65474SGeert Uytterhoeven ".*sclkdiv@.*": 38*aef65474SGeert Uytterhoeven type: object 39*aef65474SGeert Uytterhoeven 40*aef65474SGeert Uytterhoeven description: | 41*aef65474SGeert Uytterhoeven Function block with an input mux and a divider, which corresponds to 42*aef65474SGeert Uytterhoeven "Serial clock generator" in fig. "Clock System Overview" of the manual, 43*aef65474SGeert Uytterhoeven and "xxx frequency division setting register" (XXXCLKDIV) registers. 44*aef65474SGeert Uytterhoeven This makes internal (neither input nor output) clock that is provided 45*aef65474SGeert Uytterhoeven to input of xxxGCLK block. 46*aef65474SGeert Uytterhoeven 47*aef65474SGeert Uytterhoeven properties: 48*aef65474SGeert Uytterhoeven compatible: 49*aef65474SGeert Uytterhoeven const: renesas,emev2-smu-clkdiv 50*aef65474SGeert Uytterhoeven 51*aef65474SGeert Uytterhoeven reg: 52*aef65474SGeert Uytterhoeven maxItems: 1 53*aef65474SGeert Uytterhoeven description: 54*aef65474SGeert Uytterhoeven Byte offset from SMU base and Bit position in the register. 55*aef65474SGeert Uytterhoeven 56*aef65474SGeert Uytterhoeven clocks: 57*aef65474SGeert Uytterhoeven minItems: 1 58*aef65474SGeert Uytterhoeven maxItems: 4 59*aef65474SGeert Uytterhoeven 60*aef65474SGeert Uytterhoeven '#clock-cells': 61*aef65474SGeert Uytterhoeven const: 0 62*aef65474SGeert Uytterhoeven 63*aef65474SGeert Uytterhoeven required: 64*aef65474SGeert Uytterhoeven - compatible 65*aef65474SGeert Uytterhoeven - reg 66*aef65474SGeert Uytterhoeven - clocks 67*aef65474SGeert Uytterhoeven - '#clock-cells' 68*aef65474SGeert Uytterhoeven 69*aef65474SGeert Uytterhoeven additionalProperties: false 70*aef65474SGeert Uytterhoeven 71*aef65474SGeert Uytterhoeven ".*sclk@.*": 72*aef65474SGeert Uytterhoeven type: object 73*aef65474SGeert Uytterhoeven 74*aef65474SGeert Uytterhoeven description: | 75*aef65474SGeert Uytterhoeven Clock gating node shown as "Clock stop processing block" in the 76*aef65474SGeert Uytterhoeven fig. "Clock System Overview" of the manual. 77*aef65474SGeert Uytterhoeven Registers are "xxx clock gate control register" (XXXGCLKCTRL). 78*aef65474SGeert Uytterhoeven 79*aef65474SGeert Uytterhoeven properties: 80*aef65474SGeert Uytterhoeven compatible: 81*aef65474SGeert Uytterhoeven const: renesas,emev2-smu-gclk 82*aef65474SGeert Uytterhoeven 83*aef65474SGeert Uytterhoeven reg: 84*aef65474SGeert Uytterhoeven maxItems: 1 85*aef65474SGeert Uytterhoeven description: 86*aef65474SGeert Uytterhoeven Byte offset from SMU base and Bit position in the register. 87*aef65474SGeert Uytterhoeven 88*aef65474SGeert Uytterhoeven clocks: 89*aef65474SGeert Uytterhoeven maxItems: 1 90*aef65474SGeert Uytterhoeven 91*aef65474SGeert Uytterhoeven '#clock-cells': 92*aef65474SGeert Uytterhoeven const: 0 93*aef65474SGeert Uytterhoeven 94*aef65474SGeert Uytterhoeven required: 95*aef65474SGeert Uytterhoeven - compatible 96*aef65474SGeert Uytterhoeven - reg 97*aef65474SGeert Uytterhoeven - clocks 98*aef65474SGeert Uytterhoeven - '#clock-cells' 99*aef65474SGeert Uytterhoeven 100*aef65474SGeert Uytterhoeven additionalProperties: false 101*aef65474SGeert Uytterhoeven 102*aef65474SGeert UytterhoevenadditionalProperties: true 103*aef65474SGeert Uytterhoeven 104*aef65474SGeert Uytterhoevenexamples: 105*aef65474SGeert Uytterhoeven - | 106*aef65474SGeert Uytterhoeven // Example of clock-tree description: 107*aef65474SGeert Uytterhoeven // 108*aef65474SGeert Uytterhoeven // This describes a clock path in the clock tree 109*aef65474SGeert Uytterhoeven // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk 110*aef65474SGeert Uytterhoeven clocks@e0110000 { 111*aef65474SGeert Uytterhoeven compatible = "renesas,emev2-smu"; 112*aef65474SGeert Uytterhoeven reg = <0xe0110000 0x10000>; 113*aef65474SGeert Uytterhoeven #address-cells = <2>; 114*aef65474SGeert Uytterhoeven #size-cells = <0>; 115*aef65474SGeert Uytterhoeven 116*aef65474SGeert Uytterhoeven c32ki: c32ki { 117*aef65474SGeert Uytterhoeven compatible = "fixed-clock"; 118*aef65474SGeert Uytterhoeven clock-frequency = <32768>; 119*aef65474SGeert Uytterhoeven #clock-cells = <0>; 120*aef65474SGeert Uytterhoeven }; 121*aef65474SGeert Uytterhoeven pll3_fo: pll3_fo { 122*aef65474SGeert Uytterhoeven compatible = "fixed-factor-clock"; 123*aef65474SGeert Uytterhoeven clocks = <&c32ki>; 124*aef65474SGeert Uytterhoeven clock-div = <1>; 125*aef65474SGeert Uytterhoeven clock-mult = <7000>; 126*aef65474SGeert Uytterhoeven #clock-cells = <0>; 127*aef65474SGeert Uytterhoeven }; 128*aef65474SGeert Uytterhoeven usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { 129*aef65474SGeert Uytterhoeven compatible = "renesas,emev2-smu-clkdiv"; 130*aef65474SGeert Uytterhoeven reg = <0x610 0>; 131*aef65474SGeert Uytterhoeven clocks = <&pll3_fo>; 132*aef65474SGeert Uytterhoeven #clock-cells = <0>; 133*aef65474SGeert Uytterhoeven }; 134*aef65474SGeert Uytterhoeven usia_u0_sclk: usia_u0_sclk@4a0,1 { 135*aef65474SGeert Uytterhoeven compatible = "renesas,emev2-smu-gclk"; 136*aef65474SGeert Uytterhoeven reg = <0x4a0 1>; 137*aef65474SGeert Uytterhoeven clocks = <&usia_u0_sclkdiv>; 138*aef65474SGeert Uytterhoeven #clock-cells = <0>; 139*aef65474SGeert Uytterhoeven }; 140*aef65474SGeert Uytterhoeven }; 141