1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas Clock Pulse Generator / Module Standby and Software Reset
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14  and MSSR (Module Standby and Software Reset) blocks are intimately connected,
15  and share the same register block.
16
17  They provide the following functionalities:
18    - The CPG block generates various core clocks,
19    - The MSSR block provides two functions:
20        1. Module Standby, providing a Clock Domain to control the clock supply
21           to individual SoC devices,
22        2. Reset Control, to perform a software reset of individual SoC devices.
23
24properties:
25  compatible:
26    enum:
27      - renesas,r7s9210-cpg-mssr  # RZ/A2
28      - renesas,r8a7743-cpg-mssr  # RZ/G1M
29      - renesas,r8a7744-cpg-mssr  # RZ/G1N
30      - renesas,r8a7745-cpg-mssr  # RZ/G1E
31      - renesas,r8a77470-cpg-mssr # RZ/G1C
32      - renesas,r8a774a1-cpg-mssr # RZ/G2M
33      - renesas,r8a774b1-cpg-mssr # RZ/G2N
34      - renesas,r8a774c0-cpg-mssr # RZ/G2E
35      - renesas,r8a7790-cpg-mssr  # R-Car H2
36      - renesas,r8a7791-cpg-mssr  # R-Car M2-W
37      - renesas,r8a7792-cpg-mssr  # R-Car V2H
38      - renesas,r8a7793-cpg-mssr  # R-Car M2-N
39      - renesas,r8a7794-cpg-mssr  # R-Car E2
40      - renesas,r8a7795-cpg-mssr  # R-Car H3
41      - renesas,r8a7796-cpg-mssr  # R-Car M3-W
42      - renesas,r8a77961-cpg-mssr # R-Car M3-W+
43      - renesas,r8a77965-cpg-mssr # R-Car M3-N
44      - renesas,r8a77970-cpg-mssr # R-Car V3M
45      - renesas,r8a77980-cpg-mssr # R-Car V3H
46      - renesas,r8a77990-cpg-mssr # R-Car E3
47      - renesas,r8a77995-cpg-mssr # R-Car D3
48
49  reg:
50    maxItems: 1
51
52  clocks:
53    minItems: 1
54    maxItems: 2
55
56  clock-names:
57    minItems: 1
58    maxItems: 2
59    items:
60      enum:
61        - extal     # All
62        - extalr    # Most R-Car Gen3 and RZ/G2
63        - usb_extal # Most R-Car Gen2 and RZ/G1
64
65  '#clock-cells':
66    description: |
67      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
68        and a core clock reference, as defined in
69        <dt-bindings/clock/*-cpg-mssr.h>
70      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
71        a module number, as defined in the datasheet.
72    const: 2
73
74  '#power-domain-cells':
75    description:
76      SoC devices that are part of the CPG/MSSR Clock Domain and can be
77      power-managed through Module Standby should refer to the CPG device node
78      in their "power-domains" property, as documented by the generic PM Domain
79      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
80    const: 0
81
82  '#reset-cells':
83    description:
84      The single reset specifier cell must be the module number, as defined in
85      the datasheet.
86    const: 1
87
88if:
89  not:
90    properties:
91      compatible:
92        items:
93          enum:
94            - renesas,r7s9210-cpg-mssr
95then:
96  required:
97    - '#reset-cells'
98
99required:
100  - compatible
101  - reg
102  - clocks
103  - clock-names
104  - '#clock-cells'
105  - '#power-domain-cells'
106
107additionalProperties: false
108
109examples:
110  - |
111    cpg: clock-controller@e6150000 {
112            compatible = "renesas,r8a7795-cpg-mssr";
113            reg = <0xe6150000 0x1000>;
114            clocks = <&extal_clk>, <&extalr_clk>;
115            clock-names = "extal", "extalr";
116            #clock-cells = <2>;
117            #power-domain-cells = <0>;
118            #reset-cells = <1>;
119    };
120