1eeb40fdaSGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2eeb40fdaSGeert Uytterhoeven%YAML 1.2 3eeb40fdaSGeert Uytterhoeven--- 4eeb40fdaSGeert Uytterhoeven$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#" 5eeb40fdaSGeert Uytterhoeven$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6eeb40fdaSGeert Uytterhoeven 7eeb40fdaSGeert Uytterhoeventitle: Renesas Clock Pulse Generator / Module Standby and Software Reset 8eeb40fdaSGeert Uytterhoeven 9eeb40fdaSGeert Uytterhoevenmaintainers: 10eeb40fdaSGeert Uytterhoeven - Geert Uytterhoeven <geert+renesas@glider.be> 11eeb40fdaSGeert Uytterhoeven 12eeb40fdaSGeert Uytterhoevendescription: | 13eeb40fdaSGeert Uytterhoeven On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) 14eeb40fdaSGeert Uytterhoeven and MSSR (Module Standby and Software Reset) blocks are intimately connected, 15eeb40fdaSGeert Uytterhoeven and share the same register block. 16eeb40fdaSGeert Uytterhoeven 17eeb40fdaSGeert Uytterhoeven They provide the following functionalities: 18eeb40fdaSGeert Uytterhoeven - The CPG block generates various core clocks, 19eeb40fdaSGeert Uytterhoeven - The MSSR block provides two functions: 20eeb40fdaSGeert Uytterhoeven 1. Module Standby, providing a Clock Domain to control the clock supply 21eeb40fdaSGeert Uytterhoeven to individual SoC devices, 22eeb40fdaSGeert Uytterhoeven 2. Reset Control, to perform a software reset of individual SoC devices. 23eeb40fdaSGeert Uytterhoeven 24eeb40fdaSGeert Uytterhoevenproperties: 25eeb40fdaSGeert Uytterhoeven compatible: 26eeb40fdaSGeert Uytterhoeven enum: 27eeb40fdaSGeert Uytterhoeven - renesas,r7s9210-cpg-mssr # RZ/A2 2864249628SLad Prabhakar - renesas,r8a7742-cpg-mssr # RZ/G1H 29eeb40fdaSGeert Uytterhoeven - renesas,r8a7743-cpg-mssr # RZ/G1M 30eeb40fdaSGeert Uytterhoeven - renesas,r8a7744-cpg-mssr # RZ/G1N 31eeb40fdaSGeert Uytterhoeven - renesas,r8a7745-cpg-mssr # RZ/G1E 32eeb40fdaSGeert Uytterhoeven - renesas,r8a77470-cpg-mssr # RZ/G1C 33eeb40fdaSGeert Uytterhoeven - renesas,r8a774a1-cpg-mssr # RZ/G2M 34eeb40fdaSGeert Uytterhoeven - renesas,r8a774b1-cpg-mssr # RZ/G2N 35eeb40fdaSGeert Uytterhoeven - renesas,r8a774c0-cpg-mssr # RZ/G2E 36eeb40fdaSGeert Uytterhoeven - renesas,r8a7790-cpg-mssr # R-Car H2 37eeb40fdaSGeert Uytterhoeven - renesas,r8a7791-cpg-mssr # R-Car M2-W 38eeb40fdaSGeert Uytterhoeven - renesas,r8a7792-cpg-mssr # R-Car V2H 39eeb40fdaSGeert Uytterhoeven - renesas,r8a7793-cpg-mssr # R-Car M2-N 40eeb40fdaSGeert Uytterhoeven - renesas,r8a7794-cpg-mssr # R-Car E2 41eeb40fdaSGeert Uytterhoeven - renesas,r8a7795-cpg-mssr # R-Car H3 42eeb40fdaSGeert Uytterhoeven - renesas,r8a7796-cpg-mssr # R-Car M3-W 43eeb40fdaSGeert Uytterhoeven - renesas,r8a77961-cpg-mssr # R-Car M3-W+ 44eeb40fdaSGeert Uytterhoeven - renesas,r8a77965-cpg-mssr # R-Car M3-N 45eeb40fdaSGeert Uytterhoeven - renesas,r8a77970-cpg-mssr # R-Car V3M 46eeb40fdaSGeert Uytterhoeven - renesas,r8a77980-cpg-mssr # R-Car V3H 47eeb40fdaSGeert Uytterhoeven - renesas,r8a77990-cpg-mssr # R-Car E3 48eeb40fdaSGeert Uytterhoeven - renesas,r8a77995-cpg-mssr # R-Car D3 49eeb40fdaSGeert Uytterhoeven 50eeb40fdaSGeert Uytterhoeven reg: 51eeb40fdaSGeert Uytterhoeven maxItems: 1 52eeb40fdaSGeert Uytterhoeven 53eeb40fdaSGeert Uytterhoeven clocks: 54eeb40fdaSGeert Uytterhoeven minItems: 1 55eeb40fdaSGeert Uytterhoeven maxItems: 2 56eeb40fdaSGeert Uytterhoeven 57eeb40fdaSGeert Uytterhoeven clock-names: 58eeb40fdaSGeert Uytterhoeven minItems: 1 59eeb40fdaSGeert Uytterhoeven maxItems: 2 60eeb40fdaSGeert Uytterhoeven items: 61eeb40fdaSGeert Uytterhoeven enum: 62eeb40fdaSGeert Uytterhoeven - extal # All 63eeb40fdaSGeert Uytterhoeven - extalr # Most R-Car Gen3 and RZ/G2 64eeb40fdaSGeert Uytterhoeven - usb_extal # Most R-Car Gen2 and RZ/G1 65eeb40fdaSGeert Uytterhoeven 66eeb40fdaSGeert Uytterhoeven '#clock-cells': 67eeb40fdaSGeert Uytterhoeven description: | 68eeb40fdaSGeert Uytterhoeven - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 69eeb40fdaSGeert Uytterhoeven and a core clock reference, as defined in 70eeb40fdaSGeert Uytterhoeven <dt-bindings/clock/*-cpg-mssr.h> 71eeb40fdaSGeert Uytterhoeven - For module clocks, the two clock specifier cells must be "CPG_MOD" and 72eeb40fdaSGeert Uytterhoeven a module number, as defined in the datasheet. 73eeb40fdaSGeert Uytterhoeven const: 2 74eeb40fdaSGeert Uytterhoeven 75eeb40fdaSGeert Uytterhoeven '#power-domain-cells': 76eeb40fdaSGeert Uytterhoeven description: 77eeb40fdaSGeert Uytterhoeven SoC devices that are part of the CPG/MSSR Clock Domain and can be 78eeb40fdaSGeert Uytterhoeven power-managed through Module Standby should refer to the CPG device node 79eeb40fdaSGeert Uytterhoeven in their "power-domains" property, as documented by the generic PM Domain 80eeb40fdaSGeert Uytterhoeven bindings in Documentation/devicetree/bindings/power/power-domain.yaml. 81eeb40fdaSGeert Uytterhoeven const: 0 82eeb40fdaSGeert Uytterhoeven 83eeb40fdaSGeert Uytterhoeven '#reset-cells': 84eeb40fdaSGeert Uytterhoeven description: 85eeb40fdaSGeert Uytterhoeven The single reset specifier cell must be the module number, as defined in 86eeb40fdaSGeert Uytterhoeven the datasheet. 87eeb40fdaSGeert Uytterhoeven const: 1 88eeb40fdaSGeert Uytterhoeven 89eeb40fdaSGeert Uytterhoevenif: 90eeb40fdaSGeert Uytterhoeven not: 91eeb40fdaSGeert Uytterhoeven properties: 92eeb40fdaSGeert Uytterhoeven compatible: 93eeb40fdaSGeert Uytterhoeven items: 94eeb40fdaSGeert Uytterhoeven enum: 95eeb40fdaSGeert Uytterhoeven - renesas,r7s9210-cpg-mssr 96eeb40fdaSGeert Uytterhoeventhen: 97eeb40fdaSGeert Uytterhoeven required: 98eeb40fdaSGeert Uytterhoeven - '#reset-cells' 99eeb40fdaSGeert Uytterhoeven 100eeb40fdaSGeert Uytterhoevenrequired: 101eeb40fdaSGeert Uytterhoeven - compatible 102eeb40fdaSGeert Uytterhoeven - reg 103eeb40fdaSGeert Uytterhoeven - clocks 104eeb40fdaSGeert Uytterhoeven - clock-names 105eeb40fdaSGeert Uytterhoeven - '#clock-cells' 106eeb40fdaSGeert Uytterhoeven - '#power-domain-cells' 107eeb40fdaSGeert Uytterhoeven 108eeb40fdaSGeert UytterhoevenadditionalProperties: false 109eeb40fdaSGeert Uytterhoeven 110eeb40fdaSGeert Uytterhoevenexamples: 111eeb40fdaSGeert Uytterhoeven - | 112eeb40fdaSGeert Uytterhoeven cpg: clock-controller@e6150000 { 113eeb40fdaSGeert Uytterhoeven compatible = "renesas,r8a7795-cpg-mssr"; 114eeb40fdaSGeert Uytterhoeven reg = <0xe6150000 0x1000>; 115eeb40fdaSGeert Uytterhoeven clocks = <&extal_clk>, <&extalr_clk>; 116eeb40fdaSGeert Uytterhoeven clock-names = "extal", "extalr"; 117eeb40fdaSGeert Uytterhoeven #clock-cells = <2>; 118eeb40fdaSGeert Uytterhoeven #power-domain-cells = <0>; 119eeb40fdaSGeert Uytterhoeven #reset-cells = <1>; 120eeb40fdaSGeert Uytterhoeven }; 121