159e7166fSGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 259e7166fSGeert Uytterhoeven%YAML 1.2 359e7166fSGeert Uytterhoeven--- 459e7166fSGeert Uytterhoeven$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml# 559e7166fSGeert Uytterhoeven$schema: http://devicetree.org/meta-schemas/core.yaml# 659e7166fSGeert Uytterhoeven 759e7166fSGeert Uytterhoeventitle: Renesas CPG DIV6 Clock 859e7166fSGeert Uytterhoeven 959e7166fSGeert Uytterhoevenmaintainers: 1059e7166fSGeert Uytterhoeven - Geert Uytterhoeven <geert+renesas@glider.be> 1159e7166fSGeert Uytterhoeven 1259e7166fSGeert Uytterhoevendescription: 1359e7166fSGeert Uytterhoeven The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse 1459e7166fSGeert Uytterhoeven Generator (CPG). Their clock input is divided by a configurable factor from 1 1559e7166fSGeert Uytterhoeven to 64. 1659e7166fSGeert Uytterhoeven 1759e7166fSGeert Uytterhoevenproperties: 1859e7166fSGeert Uytterhoeven compatible: 1959e7166fSGeert Uytterhoeven items: 2059e7166fSGeert Uytterhoeven - enum: 2159e7166fSGeert Uytterhoeven - renesas,r8a73a4-div6-clock # R-Mobile APE6 2259e7166fSGeert Uytterhoeven - renesas,r8a7740-div6-clock # R-Mobile A1 2359e7166fSGeert Uytterhoeven - renesas,sh73a0-div6-clock # SH-Mobile AG5 2459e7166fSGeert Uytterhoeven - const: renesas,cpg-div6-clock 2559e7166fSGeert Uytterhoeven 2659e7166fSGeert Uytterhoeven reg: 2759e7166fSGeert Uytterhoeven maxItems: 1 2859e7166fSGeert Uytterhoeven 2959e7166fSGeert Uytterhoeven clocks: 3059e7166fSGeert Uytterhoeven oneOf: 3159e7166fSGeert Uytterhoeven - maxItems: 1 3259e7166fSGeert Uytterhoeven - maxItems: 4 3359e7166fSGeert Uytterhoeven - maxItems: 8 3459e7166fSGeert Uytterhoeven description: 3559e7166fSGeert Uytterhoeven For clocks with multiple parents, invalid settings must be specified as 3659e7166fSGeert Uytterhoeven "<0>". 3759e7166fSGeert Uytterhoeven 3859e7166fSGeert Uytterhoeven '#clock-cells': 3959e7166fSGeert Uytterhoeven const: 0 4059e7166fSGeert Uytterhoeven 4159e7166fSGeert Uytterhoeven clock-output-names: true 4259e7166fSGeert Uytterhoeven 4359e7166fSGeert Uytterhoevenrequired: 4459e7166fSGeert Uytterhoeven - compatible 4559e7166fSGeert Uytterhoeven - reg 4659e7166fSGeert Uytterhoeven - clocks 4759e7166fSGeert Uytterhoeven - '#clock-cells' 4859e7166fSGeert Uytterhoeven 4959e7166fSGeert UytterhoevenadditionalProperties: false 5059e7166fSGeert Uytterhoeven 5159e7166fSGeert Uytterhoevenexamples: 5259e7166fSGeert Uytterhoeven - | 5359e7166fSGeert Uytterhoeven #include <dt-bindings/clock/r8a73a4-clock.h> 5459e7166fSGeert Uytterhoeven sdhi2_clk: sdhi2_clk@e615007c { 5559e7166fSGeert Uytterhoeven compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 5659e7166fSGeert Uytterhoeven reg = <0xe615007c 4>; 5759e7166fSGeert Uytterhoeven clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, 5859e7166fSGeert Uytterhoeven <&extal2_clk>; 5959e7166fSGeert Uytterhoeven #clock-cells = <0>; 6059e7166fSGeert Uytterhoeven }; 61