1* Clock Block on Freescale QorIQ Platforms
2
3Freescale QorIQ chips take primary clocking input from the external
4SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5multiple phase locked loops (PLL) to create a variety of frequencies
6which can then be passed to a variety of internal logic, including
7cores and peripheral IP blocks.
8Please refer to the Reference Manual for details.
9
10All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11which the chip complies.
12
13Chassis Version		Example Chips
14---------------		-------------
151.0			p4080, p5020, p5040
162.0			t4240, b4860
17
181. Clock Block Binding
19
20Required properties:
21- compatible: Should contain a chip-specific clock block compatible
22	string and (if applicable) may contain a chassis-version clock
23	compatible string.
24
25	Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26	* "fsl,p2041-clockgen"
27	* "fsl,p3041-clockgen"
28	* "fsl,p4080-clockgen"
29	* "fsl,p5020-clockgen"
30	* "fsl,p5040-clockgen"
31	* "fsl,t1023-clockgen"
32	* "fsl,t1024-clockgen"
33	* "fsl,t1040-clockgen"
34	* "fsl,t1042-clockgen"
35	* "fsl,t2080-clockgen"
36	* "fsl,t2081-clockgen"
37	* "fsl,t4240-clockgen"
38	* "fsl,b4420-clockgen"
39	* "fsl,b4860-clockgen"
40	* "fsl,ls1012a-clockgen"
41	* "fsl,ls1021a-clockgen"
42	* "fsl,ls1028a-clockgen"
43	* "fsl,ls1043a-clockgen"
44	* "fsl,ls1046a-clockgen"
45	* "fsl,ls1088a-clockgen"
46	* "fsl,ls2080a-clockgen"
47	* "fsl,lx2160a-clockgen"
48	Chassis-version clock strings include:
49	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
50	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
51- reg: Describes the address of the device's resources within the
52	address space defined by its parent bus, and resource zero
53	represents the clock register set
54
55Optional properties:
56- ranges: Allows valid translation between child's address space and
57	parent's. Must be present if the device has sub-nodes.
58- #address-cells: Specifies the number of cells used to represent
59	physical base addresses.  Must be present if the device has
60	sub-nodes and set to 1 if present
61- #size-cells: Specifies the number of cells used to represent
62	the size of an address. Must be present if the device has
63	sub-nodes and set to 1 if present
64- clock-frequency: Input system clock frequency (SYSCLK)
65- clocks: If clock-frequency is not specified, sysclk may be provided
66	as an input clock.  Either clock-frequency or clocks must be
67	provided.
68	A second input clock, called "coreclk", may be provided if
69	core PLLs are based on a different input clock from the
70	platform PLL.
71- clock-names: Required if a coreclk is present.  Valid names are
72	"sysclk" and "coreclk".
73
742. Clock Provider
75
76The clockgen node should act as a clock provider, though in older device
77trees the children of the clockgen node are the clock providers.
78
79When the clockgen node is a clock provider, #clock-cells = <2>.
80The first cell of the clock specifier is the clock type, and the
81second cell is the clock index for the specified type.
82
83	Type#	Name		Index Cell
84	0	sysclk		must be 0
85	1	cmux		index (n in CLKCnCSR)
86	2	hwaccel		index (n in CLKCGnHWACSR)
87	3	fman		0 for fm1, 1 for fm2
88	4	platform pll	n=pll/(n+1). For example, when n=1,
89				that means output_freq=PLL_freq/2.
90	5	coreclk		must be 0
91
923. Example
93
94	clockgen: global-utilities@e1000 {
95		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
96		clock-frequency = <133333333>;
97		reg = <0xe1000 0x1000>;
98		#clock-cells = <2>;
99	};
100
101	fman@400000 {
102		...
103		clocks = <&clockgen 3 0>;
104		...
105	};
106}
1074. Legacy Child Nodes
108
109NOTE: These nodes are deprecated.  Kernels should continue to support
110device trees with these nodes, but new device trees should not use them.
111
112Most of the bindings are from the common clock binding[1].
113 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
114
115Required properties:
116- compatible : Should include one of the following:
117	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
118	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
119	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
120	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
121	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
122		It takes parent's clock-frequency as its clock.
123	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
124		It takes parent's clock-frequency as its clock.
125	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
126	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
127- #clock-cells: From common clock binding. The number of cells in a
128	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
129	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
130	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
131	clock-specifier cell may take the following values:
132	* 0 - equal to the PLL frequency
133	* 1 - equal to the PLL frequency divided by 2
134	* 2 - equal to the PLL frequency divided by 4
135
136Recommended properties:
137- clocks: Should be the phandle of input parent clock
138- clock-names: From common clock binding, indicates the clock name
139- clock-output-names: From common clock binding, indicates the names of
140	output clocks
141- reg: Should be the offset and length of clock block base address.
142	The length should be 4.
143
144Legacy Example:
145/ {
146	clockgen: global-utilities@e1000 {
147		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
148		ranges = <0x0 0xe1000 0x1000>;
149		clock-frequency = <133333333>;
150		reg = <0xe1000 0x1000>;
151		#address-cells = <1>;
152		#size-cells = <1>;
153
154		sysclk: sysclk {
155			#clock-cells = <0>;
156			compatible = "fsl,qoriq-sysclk-1.0";
157			clock-output-names = "sysclk";
158		};
159
160		pll0: pll0@800 {
161			#clock-cells = <1>;
162			reg = <0x800 0x4>;
163			compatible = "fsl,qoriq-core-pll-1.0";
164			clocks = <&sysclk>;
165			clock-output-names = "pll0", "pll0-div2";
166		};
167
168		pll1: pll1@820 {
169			#clock-cells = <1>;
170			reg = <0x820 0x4>;
171			compatible = "fsl,qoriq-core-pll-1.0";
172			clocks = <&sysclk>;
173			clock-output-names = "pll1", "pll1-div2";
174		};
175
176		mux0: mux0@0 {
177			#clock-cells = <0>;
178			reg = <0x0 0x4>;
179			compatible = "fsl,qoriq-core-mux-1.0";
180			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
181			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
182			clock-output-names = "cmux0";
183		};
184
185		mux1: mux1@20 {
186			#clock-cells = <0>;
187			reg = <0x20 0x4>;
188			compatible = "fsl,qoriq-core-mux-1.0";
189			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
190			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
191			clock-output-names = "cmux1";
192		};
193
194		platform-pll: platform-pll@c00 {
195			#clock-cells = <1>;
196			reg = <0xc00 0x4>;
197			compatible = "fsl,qoriq-platform-pll-1.0";
198			clocks = <&sysclk>;
199			clock-output-names = "platform-pll", "platform-pll-div2";
200		};
201	};
202};
203
204Example for legacy clock consumer:
205
206/ {
207	cpu0: PowerPC,e5500@0 {
208		...
209		clocks = <&mux0>;
210		...
211	};
212};
213