1* Clock Block on Freescale CoreNet Platforms
2
3Freescale CoreNet chips take primary clocking input from the external
4SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5multiple phase locked loops (PLL) to create a variety of frequencies
6which can then be passed to a variety of internal logic, including
7cores and peripheral IP blocks.
8Please refer to the Reference Manual for details.
9
10All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11which the chip complies.
12
13Chassis Version		Example Chips
14---------------		-------------
151.0			p4080, p5020, p5040
162.0			t4240, b4860, t1040
17
181. Clock Block Binding
19
20Required properties:
21- compatible: Should contain a specific clock block compatible string
22	and a single chassis clock compatible string.
23	Clock block strings include, but not limited to, one of the:
24	* "fsl,p2041-clockgen"
25	* "fsl,p3041-clockgen"
26	* "fsl,p4080-clockgen"
27	* "fsl,p5020-clockgen"
28	* "fsl,p5040-clockgen"
29	* "fsl,t4240-clockgen"
30	* "fsl,b4420-clockgen"
31	* "fsl,b4860-clockgen"
32	Chassis clock strings include:
33	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
34	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
35- reg: Describes the address of the device's resources within the
36	address space defined by its parent bus, and resource zero
37	represents the clock register set
38- clock-frequency: Input system clock frequency
39
40Recommended properties:
41- ranges: Allows valid translation between child's address space and
42	parent's. Must be present if the device has sub-nodes.
43- #address-cells: Specifies the number of cells used to represent
44	physical base addresses.  Must be present if the device has
45	sub-nodes and set to 1 if present
46- #size-cells: Specifies the number of cells used to represent
47	the size of an address. Must be present if the device has
48	sub-nodes and set to 1 if present
49
502. Clock Provider/Consumer Binding
51
52Most of the bindings are from the common clock binding[1].
53 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
54
55Required properties:
56- compatible : Should include one of the following:
57	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
58	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
59	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
60	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
61	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
62		It takes parent's clock-frequency as its clock.
63	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
64		It takes parent's clock-frequency as its clock.
65	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
66	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
67- #clock-cells: From common clock binding. The number of cells in a
68	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
69	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
70	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
71	clock-specifier cell may take the following values:
72	* 0 - equal to the PLL frequency
73	* 1 - equal to the PLL frequency divided by 2
74	* 2 - equal to the PLL frequency divided by 4
75
76Recommended properties:
77- clocks: Should be the phandle of input parent clock
78- clock-names: From common clock binding, indicates the clock name
79- clock-output-names: From common clock binding, indicates the names of
80	output clocks
81- reg: Should be the offset and length of clock block base address.
82	The length should be 4.
83
84Example for clock block and clock provider:
85/ {
86	clockgen: global-utilities@e1000 {
87		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
88		ranges = <0x0 0xe1000 0x1000>;
89		clock-frequency = <133333333>;
90		reg = <0xe1000 0x1000>;
91		#address-cells = <1>;
92		#size-cells = <1>;
93
94		sysclk: sysclk {
95			#clock-cells = <0>;
96			compatible = "fsl,qoriq-sysclk-1.0";
97			clock-output-names = "sysclk";
98		};
99
100		pll0: pll0@800 {
101			#clock-cells = <1>;
102			reg = <0x800 0x4>;
103			compatible = "fsl,qoriq-core-pll-1.0";
104			clocks = <&sysclk>;
105			clock-output-names = "pll0", "pll0-div2";
106		};
107
108		pll1: pll1@820 {
109			#clock-cells = <1>;
110			reg = <0x820 0x4>;
111			compatible = "fsl,qoriq-core-pll-1.0";
112			clocks = <&sysclk>;
113			clock-output-names = "pll1", "pll1-div2";
114		};
115
116		mux0: mux0@0 {
117			#clock-cells = <0>;
118			reg = <0x0 0x4>;
119			compatible = "fsl,qoriq-core-mux-1.0";
120			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
121			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
122			clock-output-names = "cmux0";
123		};
124
125		mux1: mux1@20 {
126			#clock-cells = <0>;
127			reg = <0x20 0x4>;
128			compatible = "fsl,qoriq-core-mux-1.0";
129			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
130			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
131			clock-output-names = "cmux1";
132		};
133
134		platform-pll: platform-pll@c00 {
135			#clock-cells = <1>;
136			reg = <0xc00 0x4>;
137			compatible = "fsl,qoriq-platform-pll-1.0";
138			clocks = <&sysclk>;
139			clock-output-names = "platform-pll", "platform-pll-div2";
140		};
141	};
142};
143
144Example for clock consumer:
145
146/ {
147	cpu0: PowerPC,e5500@0 {
148		...
149		clocks = <&mux0>;
150		...
151	};
152};
153