1* Clock Block on Freescale QorIQ Platforms
2
3Freescale QorIQ chips take primary clocking input from the external
4SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5multiple phase locked loops (PLL) to create a variety of frequencies
6which can then be passed to a variety of internal logic, including
7cores and peripheral IP blocks.
8Please refer to the Reference Manual for details.
9
10All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11which the chip complies.
12
13Chassis Version		Example Chips
14---------------		-------------
151.0			p4080, p5020, p5040
162.0			t4240, b4860
17
181. Clock Block Binding
19
20Required properties:
21- compatible: Should contain a chip-specific clock block compatible
22	string and (if applicable) may contain a chassis-version clock
23	compatible string.
24
25	Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26	* "fsl,p2041-clockgen"
27	* "fsl,p3041-clockgen"
28	* "fsl,p4080-clockgen"
29	* "fsl,p5020-clockgen"
30	* "fsl,p5040-clockgen"
31	* "fsl,t4240-clockgen"
32	* "fsl,b4420-clockgen"
33	* "fsl,b4860-clockgen"
34	* "fsl,ls1012a-clockgen"
35	* "fsl,ls1021a-clockgen"
36	* "fsl,ls1043a-clockgen"
37	* "fsl,ls1046a-clockgen"
38	* "fsl,ls2080a-clockgen"
39	Chassis-version clock strings include:
40	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
41	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
42- reg: Describes the address of the device's resources within the
43	address space defined by its parent bus, and resource zero
44	represents the clock register set
45
46Optional properties:
47- ranges: Allows valid translation between child's address space and
48	parent's. Must be present if the device has sub-nodes.
49- #address-cells: Specifies the number of cells used to represent
50	physical base addresses.  Must be present if the device has
51	sub-nodes and set to 1 if present
52- #size-cells: Specifies the number of cells used to represent
53	the size of an address. Must be present if the device has
54	sub-nodes and set to 1 if present
55- clock-frequency: Input system clock frequency (SYSCLK)
56- clocks: If clock-frequency is not specified, sysclk may be provided
57	as an input clock.  Either clock-frequency or clocks must be
58	provided.
59
602. Clock Provider
61
62The clockgen node should act as a clock provider, though in older device
63trees the children of the clockgen node are the clock providers.
64
65When the clockgen node is a clock provider, #clock-cells = <2>.
66The first cell of the clock specifier is the clock type, and the
67second cell is the clock index for the specified type.
68
69	Type#	Name		Index Cell
70	0	sysclk		must be 0
71	1	cmux		index (n in CLKCnCSR)
72	2	hwaccel		index (n in CLKCGnHWACSR)
73	3	fman		0 for fm1, 1 for fm2
74	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
75
763. Example
77
78	clockgen: global-utilities@e1000 {
79		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
80		clock-frequency = <133333333>;
81		reg = <0xe1000 0x1000>;
82		#clock-cells = <2>;
83	};
84
85	fman@400000 {
86		...
87		clocks = <&clockgen 3 0>;
88		...
89	};
90}
914. Legacy Child Nodes
92
93NOTE: These nodes are deprecated.  Kernels should continue to support
94device trees with these nodes, but new device trees should not use them.
95
96Most of the bindings are from the common clock binding[1].
97 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
98
99Required properties:
100- compatible : Should include one of the following:
101	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
102	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
103	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
104	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
105	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
106		It takes parent's clock-frequency as its clock.
107	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
108		It takes parent's clock-frequency as its clock.
109	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
110	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
111- #clock-cells: From common clock binding. The number of cells in a
112	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
113	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
114	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
115	clock-specifier cell may take the following values:
116	* 0 - equal to the PLL frequency
117	* 1 - equal to the PLL frequency divided by 2
118	* 2 - equal to the PLL frequency divided by 4
119
120Recommended properties:
121- clocks: Should be the phandle of input parent clock
122- clock-names: From common clock binding, indicates the clock name
123- clock-output-names: From common clock binding, indicates the names of
124	output clocks
125- reg: Should be the offset and length of clock block base address.
126	The length should be 4.
127
128Legacy Example:
129/ {
130	clockgen: global-utilities@e1000 {
131		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
132		ranges = <0x0 0xe1000 0x1000>;
133		clock-frequency = <133333333>;
134		reg = <0xe1000 0x1000>;
135		#address-cells = <1>;
136		#size-cells = <1>;
137
138		sysclk: sysclk {
139			#clock-cells = <0>;
140			compatible = "fsl,qoriq-sysclk-1.0";
141			clock-output-names = "sysclk";
142		};
143
144		pll0: pll0@800 {
145			#clock-cells = <1>;
146			reg = <0x800 0x4>;
147			compatible = "fsl,qoriq-core-pll-1.0";
148			clocks = <&sysclk>;
149			clock-output-names = "pll0", "pll0-div2";
150		};
151
152		pll1: pll1@820 {
153			#clock-cells = <1>;
154			reg = <0x820 0x4>;
155			compatible = "fsl,qoriq-core-pll-1.0";
156			clocks = <&sysclk>;
157			clock-output-names = "pll1", "pll1-div2";
158		};
159
160		mux0: mux0@0 {
161			#clock-cells = <0>;
162			reg = <0x0 0x4>;
163			compatible = "fsl,qoriq-core-mux-1.0";
164			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
165			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
166			clock-output-names = "cmux0";
167		};
168
169		mux1: mux1@20 {
170			#clock-cells = <0>;
171			reg = <0x20 0x4>;
172			compatible = "fsl,qoriq-core-mux-1.0";
173			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
174			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
175			clock-output-names = "cmux1";
176		};
177
178		platform-pll: platform-pll@c00 {
179			#clock-cells = <1>;
180			reg = <0xc00 0x4>;
181			compatible = "fsl,qoriq-platform-pll-1.0";
182			clocks = <&sysclk>;
183			clock-output-names = "platform-pll", "platform-pll-div2";
184		};
185	};
186};
187
188Example for legacy clock consumer:
189
190/ {
191	cpu0: PowerPC,e5500@0 {
192		...
193		clocks = <&mux0>;
194		...
195	};
196};
197