1* Clock Block on Freescale QorIQ Platforms
2
3Freescale QorIQ chips take primary clocking input from the external
4SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5multiple phase locked loops (PLL) to create a variety of frequencies
6which can then be passed to a variety of internal logic, including
7cores and peripheral IP blocks.
8Please refer to the Reference Manual for details.
9
10All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11which the chip complies.
12
13Chassis Version		Example Chips
14---------------		-------------
151.0			p4080, p5020, p5040
162.0			t4240, b4860
17
181. Clock Block Binding
19
20Required properties:
21- compatible: Should contain a chip-specific clock block compatible
22	string and (if applicable) may contain a chassis-version clock
23	compatible string.
24
25	Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26	* "fsl,p2041-clockgen"
27	* "fsl,p3041-clockgen"
28	* "fsl,p4080-clockgen"
29	* "fsl,p5020-clockgen"
30	* "fsl,p5040-clockgen"
31	* "fsl,t4240-clockgen"
32	* "fsl,b4420-clockgen"
33	* "fsl,b4860-clockgen"
34	* "fsl,ls1012a-clockgen"
35	* "fsl,ls1021a-clockgen"
36	* "fsl,ls1043a-clockgen"
37	* "fsl,ls1046a-clockgen"
38	* "fsl,ls1088a-clockgen"
39	* "fsl,ls2080a-clockgen"
40	Chassis-version clock strings include:
41	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
42	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
43- reg: Describes the address of the device's resources within the
44	address space defined by its parent bus, and resource zero
45	represents the clock register set
46
47Optional properties:
48- ranges: Allows valid translation between child's address space and
49	parent's. Must be present if the device has sub-nodes.
50- #address-cells: Specifies the number of cells used to represent
51	physical base addresses.  Must be present if the device has
52	sub-nodes and set to 1 if present
53- #size-cells: Specifies the number of cells used to represent
54	the size of an address. Must be present if the device has
55	sub-nodes and set to 1 if present
56- clock-frequency: Input system clock frequency (SYSCLK)
57- clocks: If clock-frequency is not specified, sysclk may be provided
58	as an input clock.  Either clock-frequency or clocks must be
59	provided.
60	A second input clock, called "coreclk", may be provided if
61	core PLLs are based on a different input clock from the
62	platform PLL.
63- clock-names: Required if a coreclk is present.  Valid names are
64	"sysclk" and "coreclk".
65
662. Clock Provider
67
68The clockgen node should act as a clock provider, though in older device
69trees the children of the clockgen node are the clock providers.
70
71When the clockgen node is a clock provider, #clock-cells = <2>.
72The first cell of the clock specifier is the clock type, and the
73second cell is the clock index for the specified type.
74
75	Type#	Name		Index Cell
76	0	sysclk		must be 0
77	1	cmux		index (n in CLKCnCSR)
78	2	hwaccel		index (n in CLKCGnHWACSR)
79	3	fman		0 for fm1, 1 for fm2
80	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
81	5	coreclk		must be 0
82
833. Example
84
85	clockgen: global-utilities@e1000 {
86		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
87		clock-frequency = <133333333>;
88		reg = <0xe1000 0x1000>;
89		#clock-cells = <2>;
90	};
91
92	fman@400000 {
93		...
94		clocks = <&clockgen 3 0>;
95		...
96	};
97}
984. Legacy Child Nodes
99
100NOTE: These nodes are deprecated.  Kernels should continue to support
101device trees with these nodes, but new device trees should not use them.
102
103Most of the bindings are from the common clock binding[1].
104 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
105
106Required properties:
107- compatible : Should include one of the following:
108	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
109	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
110	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
111	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
112	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
113		It takes parent's clock-frequency as its clock.
114	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
115		It takes parent's clock-frequency as its clock.
116	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
117	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
118- #clock-cells: From common clock binding. The number of cells in a
119	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
120	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
121	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
122	clock-specifier cell may take the following values:
123	* 0 - equal to the PLL frequency
124	* 1 - equal to the PLL frequency divided by 2
125	* 2 - equal to the PLL frequency divided by 4
126
127Recommended properties:
128- clocks: Should be the phandle of input parent clock
129- clock-names: From common clock binding, indicates the clock name
130- clock-output-names: From common clock binding, indicates the names of
131	output clocks
132- reg: Should be the offset and length of clock block base address.
133	The length should be 4.
134
135Legacy Example:
136/ {
137	clockgen: global-utilities@e1000 {
138		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
139		ranges = <0x0 0xe1000 0x1000>;
140		clock-frequency = <133333333>;
141		reg = <0xe1000 0x1000>;
142		#address-cells = <1>;
143		#size-cells = <1>;
144
145		sysclk: sysclk {
146			#clock-cells = <0>;
147			compatible = "fsl,qoriq-sysclk-1.0";
148			clock-output-names = "sysclk";
149		};
150
151		pll0: pll0@800 {
152			#clock-cells = <1>;
153			reg = <0x800 0x4>;
154			compatible = "fsl,qoriq-core-pll-1.0";
155			clocks = <&sysclk>;
156			clock-output-names = "pll0", "pll0-div2";
157		};
158
159		pll1: pll1@820 {
160			#clock-cells = <1>;
161			reg = <0x820 0x4>;
162			compatible = "fsl,qoriq-core-pll-1.0";
163			clocks = <&sysclk>;
164			clock-output-names = "pll1", "pll1-div2";
165		};
166
167		mux0: mux0@0 {
168			#clock-cells = <0>;
169			reg = <0x0 0x4>;
170			compatible = "fsl,qoriq-core-mux-1.0";
171			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
172			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
173			clock-output-names = "cmux0";
174		};
175
176		mux1: mux1@20 {
177			#clock-cells = <0>;
178			reg = <0x20 0x4>;
179			compatible = "fsl,qoriq-core-mux-1.0";
180			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
181			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
182			clock-output-names = "cmux1";
183		};
184
185		platform-pll: platform-pll@c00 {
186			#clock-cells = <1>;
187			reg = <0xc00 0x4>;
188			compatible = "fsl,qoriq-platform-pll-1.0";
189			clocks = <&sysclk>;
190			clock-output-names = "platform-pll", "platform-pll-div2";
191		};
192	};
193};
194
195Example for legacy clock consumer:
196
197/ {
198	cpu0: PowerPC,e5500@0 {
199		...
200		clocks = <&mux0>;
201		...
202	};
203};
204