193a17c05STang Yuantian* Clock Block on Freescale QorIQ Platforms 2eaf76b21STang Yuantian 30dfc86b3SScott WoodFreescale QorIQ chips take primary clocking input from the external 4eaf76b21STang YuantianSYSCLK signal. The SYSCLK input (frequency) is multiplied using 5eaf76b21STang Yuantianmultiple phase locked loops (PLL) to create a variety of frequencies 6eaf76b21STang Yuantianwhich can then be passed to a variety of internal logic, including 7eaf76b21STang Yuantiancores and peripheral IP blocks. 8eaf76b21STang YuantianPlease refer to the Reference Manual for details. 9eaf76b21STang Yuantian 10eaf76b21STang YuantianAll references to "1.0" and "2.0" refer to the QorIQ chassis version to 11eaf76b21STang Yuantianwhich the chip complies. 12eaf76b21STang Yuantian 13eaf76b21STang YuantianChassis Version Example Chips 14eaf76b21STang Yuantian--------------- ------------- 15eaf76b21STang Yuantian1.0 p4080, p5020, p5040 160dfc86b3SScott Wood2.0 t4240, b4860 17eaf76b21STang Yuantian 18eaf76b21STang Yuantian1. Clock Block Binding 19eaf76b21STang Yuantian 20eaf76b21STang YuantianRequired properties: 210dfc86b3SScott Wood- compatible: Should contain a chip-specific clock block compatible 220dfc86b3SScott Wood string and (if applicable) may contain a chassis-version clock 230dfc86b3SScott Wood compatible string. 240dfc86b3SScott Wood 250dfc86b3SScott Wood Chip-specific strings are of the form "fsl,<chip>-clockgen", such as: 26eaf76b21STang Yuantian * "fsl,p2041-clockgen" 27eaf76b21STang Yuantian * "fsl,p3041-clockgen" 28eaf76b21STang Yuantian * "fsl,p4080-clockgen" 29eaf76b21STang Yuantian * "fsl,p5020-clockgen" 30eaf76b21STang Yuantian * "fsl,p5040-clockgen" 31a6ee0c00SYuantian Tang * "fsl,t1023-clockgen" 32a6ee0c00SYuantian Tang * "fsl,t1024-clockgen" 33a6ee0c00SYuantian Tang * "fsl,t1040-clockgen" 34a6ee0c00SYuantian Tang * "fsl,t1042-clockgen" 35a6ee0c00SYuantian Tang * "fsl,t2080-clockgen" 36a6ee0c00SYuantian Tang * "fsl,t2081-clockgen" 37eaf76b21STang Yuantian * "fsl,t4240-clockgen" 38eaf76b21STang Yuantian * "fsl,b4420-clockgen" 39eaf76b21STang Yuantian * "fsl,b4860-clockgen" 4073447f68SHarninder Rai * "fsl,ls1012a-clockgen" 4193a17c05STang Yuantian * "fsl,ls1021a-clockgen" 422b688d5bSShaohui Xie * "fsl,ls1043a-clockgen" 432b688d5bSShaohui Xie * "fsl,ls1046a-clockgen" 44124248e2SHarninder Rai * "fsl,ls1088a-clockgen" 452b688d5bSShaohui Xie * "fsl,ls2080a-clockgen" 460dfc86b3SScott Wood Chassis-version clock strings include: 47eaf76b21STang Yuantian * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks 48eaf76b21STang Yuantian * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks 49eaf76b21STang Yuantian- reg: Describes the address of the device's resources within the 50eaf76b21STang Yuantian address space defined by its parent bus, and resource zero 51eaf76b21STang Yuantian represents the clock register set 52eaf76b21STang Yuantian 530dfc86b3SScott WoodOptional properties: 54eaf76b21STang Yuantian- ranges: Allows valid translation between child's address space and 55eaf76b21STang Yuantian parent's. Must be present if the device has sub-nodes. 56eaf76b21STang Yuantian- #address-cells: Specifies the number of cells used to represent 57eaf76b21STang Yuantian physical base addresses. Must be present if the device has 58eaf76b21STang Yuantian sub-nodes and set to 1 if present 59eaf76b21STang Yuantian- #size-cells: Specifies the number of cells used to represent 60eaf76b21STang Yuantian the size of an address. Must be present if the device has 61eaf76b21STang Yuantian sub-nodes and set to 1 if present 620dfc86b3SScott Wood- clock-frequency: Input system clock frequency (SYSCLK) 630dfc86b3SScott Wood- clocks: If clock-frequency is not specified, sysclk may be provided 640dfc86b3SScott Wood as an input clock. Either clock-frequency or clocks must be 650dfc86b3SScott Wood provided. 663d362b1fSScott Wood A second input clock, called "coreclk", may be provided if 673d362b1fSScott Wood core PLLs are based on a different input clock from the 683d362b1fSScott Wood platform PLL. 693d362b1fSScott Wood- clock-names: Required if a coreclk is present. Valid names are 703d362b1fSScott Wood "sysclk" and "coreclk". 71eaf76b21STang Yuantian 720dfc86b3SScott Wood2. Clock Provider 730dfc86b3SScott Wood 740dfc86b3SScott WoodThe clockgen node should act as a clock provider, though in older device 750dfc86b3SScott Woodtrees the children of the clockgen node are the clock providers. 760dfc86b3SScott Wood 770dfc86b3SScott WoodWhen the clockgen node is a clock provider, #clock-cells = <2>. 780dfc86b3SScott WoodThe first cell of the clock specifier is the clock type, and the 790dfc86b3SScott Woodsecond cell is the clock index for the specified type. 800dfc86b3SScott Wood 810dfc86b3SScott Wood Type# Name Index Cell 820dfc86b3SScott Wood 0 sysclk must be 0 830dfc86b3SScott Wood 1 cmux index (n in CLKCnCSR) 840dfc86b3SScott Wood 2 hwaccel index (n in CLKCGnHWACSR) 850dfc86b3SScott Wood 3 fman 0 for fm1, 1 for fm2 86f34b2c26SYuantian Tang 4 platform pll n=pll/(n+1). For example, when n=1, 87f34b2c26SYuantian Tang that means output_freq=PLL_freq/2. 883d362b1fSScott Wood 5 coreclk must be 0 890dfc86b3SScott Wood 900dfc86b3SScott Wood3. Example 910dfc86b3SScott Wood 920dfc86b3SScott Wood clockgen: global-utilities@e1000 { 930dfc86b3SScott Wood compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 940dfc86b3SScott Wood clock-frequency = <133333333>; 950dfc86b3SScott Wood reg = <0xe1000 0x1000>; 960dfc86b3SScott Wood #clock-cells = <2>; 970dfc86b3SScott Wood }; 980dfc86b3SScott Wood 990dfc86b3SScott Wood fman@400000 { 1000dfc86b3SScott Wood ... 1010dfc86b3SScott Wood clocks = <&clockgen 3 0>; 1020dfc86b3SScott Wood ... 1030dfc86b3SScott Wood }; 1040dfc86b3SScott Wood} 1050dfc86b3SScott Wood4. Legacy Child Nodes 1060dfc86b3SScott Wood 1070dfc86b3SScott WoodNOTE: These nodes are deprecated. Kernels should continue to support 1080dfc86b3SScott Wooddevice trees with these nodes, but new device trees should not use them. 109eaf76b21STang Yuantian 110eaf76b21STang YuantianMost of the bindings are from the common clock binding[1]. 111eaf76b21STang Yuantian [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 112eaf76b21STang Yuantian 113eaf76b21STang YuantianRequired properties: 114eaf76b21STang Yuantian- compatible : Should include one of the following: 115eaf76b21STang Yuantian * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) 116eaf76b21STang Yuantian * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) 117eaf76b21STang Yuantian * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) 118eaf76b21STang Yuantian * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) 119eaf76b21STang Yuantian * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). 120eaf76b21STang Yuantian It takes parent's clock-frequency as its clock. 121eaf76b21STang Yuantian * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). 122eaf76b21STang Yuantian It takes parent's clock-frequency as its clock. 123f1aa77c9SEmil Medve * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) 124f1aa77c9SEmil Medve * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) 125eaf76b21STang Yuantian- #clock-cells: From common clock binding. The number of cells in a 126eaf76b21STang Yuantian clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" 127eaf76b21STang Yuantian clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. 128eaf76b21STang Yuantian For "fsl,qoriq-core-pll-[1,2].0" clocks, the single 129eaf76b21STang Yuantian clock-specifier cell may take the following values: 130eaf76b21STang Yuantian * 0 - equal to the PLL frequency 131eaf76b21STang Yuantian * 1 - equal to the PLL frequency divided by 2 132eaf76b21STang Yuantian * 2 - equal to the PLL frequency divided by 4 133eaf76b21STang Yuantian 134eaf76b21STang YuantianRecommended properties: 135eaf76b21STang Yuantian- clocks: Should be the phandle of input parent clock 136eaf76b21STang Yuantian- clock-names: From common clock binding, indicates the clock name 137eaf76b21STang Yuantian- clock-output-names: From common clock binding, indicates the names of 138eaf76b21STang Yuantian output clocks 139eaf76b21STang Yuantian- reg: Should be the offset and length of clock block base address. 140eaf76b21STang Yuantian The length should be 4. 141eaf76b21STang Yuantian 1420dfc86b3SScott WoodLegacy Example: 143eaf76b21STang Yuantian/ { 144eaf76b21STang Yuantian clockgen: global-utilities@e1000 { 145eaf76b21STang Yuantian compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 146eaf76b21STang Yuantian ranges = <0x0 0xe1000 0x1000>; 147eaf76b21STang Yuantian clock-frequency = <133333333>; 148eaf76b21STang Yuantian reg = <0xe1000 0x1000>; 149eaf76b21STang Yuantian #address-cells = <1>; 150eaf76b21STang Yuantian #size-cells = <1>; 151eaf76b21STang Yuantian 152eaf76b21STang Yuantian sysclk: sysclk { 153eaf76b21STang Yuantian #clock-cells = <0>; 154eaf76b21STang Yuantian compatible = "fsl,qoriq-sysclk-1.0"; 155eaf76b21STang Yuantian clock-output-names = "sysclk"; 156eaf76b21STang Yuantian }; 157eaf76b21STang Yuantian 158eaf76b21STang Yuantian pll0: pll0@800 { 159eaf76b21STang Yuantian #clock-cells = <1>; 160eaf76b21STang Yuantian reg = <0x800 0x4>; 161eaf76b21STang Yuantian compatible = "fsl,qoriq-core-pll-1.0"; 162eaf76b21STang Yuantian clocks = <&sysclk>; 163eaf76b21STang Yuantian clock-output-names = "pll0", "pll0-div2"; 164eaf76b21STang Yuantian }; 165eaf76b21STang Yuantian 166eaf76b21STang Yuantian pll1: pll1@820 { 167eaf76b21STang Yuantian #clock-cells = <1>; 168eaf76b21STang Yuantian reg = <0x820 0x4>; 169eaf76b21STang Yuantian compatible = "fsl,qoriq-core-pll-1.0"; 170eaf76b21STang Yuantian clocks = <&sysclk>; 171eaf76b21STang Yuantian clock-output-names = "pll1", "pll1-div2"; 172eaf76b21STang Yuantian }; 173eaf76b21STang Yuantian 174eaf76b21STang Yuantian mux0: mux0@0 { 175eaf76b21STang Yuantian #clock-cells = <0>; 176eaf76b21STang Yuantian reg = <0x0 0x4>; 177eaf76b21STang Yuantian compatible = "fsl,qoriq-core-mux-1.0"; 178eaf76b21STang Yuantian clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 179eaf76b21STang Yuantian clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 180eaf76b21STang Yuantian clock-output-names = "cmux0"; 181eaf76b21STang Yuantian }; 182eaf76b21STang Yuantian 183eaf76b21STang Yuantian mux1: mux1@20 { 184eaf76b21STang Yuantian #clock-cells = <0>; 185eaf76b21STang Yuantian reg = <0x20 0x4>; 186eaf76b21STang Yuantian compatible = "fsl,qoriq-core-mux-1.0"; 187eaf76b21STang Yuantian clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 188eaf76b21STang Yuantian clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 189eaf76b21STang Yuantian clock-output-names = "cmux1"; 190eaf76b21STang Yuantian }; 191f1aa77c9SEmil Medve 192f1aa77c9SEmil Medve platform-pll: platform-pll@c00 { 193f1aa77c9SEmil Medve #clock-cells = <1>; 194f1aa77c9SEmil Medve reg = <0xc00 0x4>; 195f1aa77c9SEmil Medve compatible = "fsl,qoriq-platform-pll-1.0"; 196f1aa77c9SEmil Medve clocks = <&sysclk>; 197f1aa77c9SEmil Medve clock-output-names = "platform-pll", "platform-pll-div2"; 198eaf76b21STang Yuantian }; 199f1aa77c9SEmil Medve }; 200f1aa77c9SEmil Medve}; 201eaf76b21STang Yuantian 2020dfc86b3SScott WoodExample for legacy clock consumer: 203eaf76b21STang Yuantian 204eaf76b21STang Yuantian/ { 205eaf76b21STang Yuantian cpu0: PowerPC,e5500@0 { 206eaf76b21STang Yuantian ... 207eaf76b21STang Yuantian clocks = <&mux0>; 208eaf76b21STang Yuantian ... 209eaf76b21STang Yuantian }; 210f1aa77c9SEmil Medve}; 211