1eaf76b21STang Yuantian* Clock Block on Freescale CoreNet Platforms 2eaf76b21STang Yuantian 3eaf76b21STang YuantianFreescale CoreNet chips take primary clocking input from the external 4eaf76b21STang YuantianSYSCLK signal. The SYSCLK input (frequency) is multiplied using 5eaf76b21STang Yuantianmultiple phase locked loops (PLL) to create a variety of frequencies 6eaf76b21STang Yuantianwhich can then be passed to a variety of internal logic, including 7eaf76b21STang Yuantiancores and peripheral IP blocks. 8eaf76b21STang YuantianPlease refer to the Reference Manual for details. 9eaf76b21STang Yuantian 10eaf76b21STang YuantianAll references to "1.0" and "2.0" refer to the QorIQ chassis version to 11eaf76b21STang Yuantianwhich the chip complies. 12eaf76b21STang Yuantian 13eaf76b21STang YuantianChassis Version Example Chips 14eaf76b21STang Yuantian--------------- ------------- 15eaf76b21STang Yuantian1.0 p4080, p5020, p5040 16eaf76b21STang Yuantian2.0 t4240, b4860, t1040 17eaf76b21STang Yuantian 18eaf76b21STang Yuantian1. Clock Block Binding 19eaf76b21STang Yuantian 20eaf76b21STang YuantianRequired properties: 21eaf76b21STang Yuantian- compatible: Should contain a specific clock block compatible string 22eaf76b21STang Yuantian and a single chassis clock compatible string. 23eaf76b21STang Yuantian Clock block strings include, but not limited to, one of the: 24eaf76b21STang Yuantian * "fsl,p2041-clockgen" 25eaf76b21STang Yuantian * "fsl,p3041-clockgen" 26eaf76b21STang Yuantian * "fsl,p4080-clockgen" 27eaf76b21STang Yuantian * "fsl,p5020-clockgen" 28eaf76b21STang Yuantian * "fsl,p5040-clockgen" 29eaf76b21STang Yuantian * "fsl,t4240-clockgen" 30eaf76b21STang Yuantian * "fsl,b4420-clockgen" 31eaf76b21STang Yuantian * "fsl,b4860-clockgen" 32eaf76b21STang Yuantian Chassis clock strings include: 33eaf76b21STang Yuantian * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks 34eaf76b21STang Yuantian * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks 35eaf76b21STang Yuantian- reg: Describes the address of the device's resources within the 36eaf76b21STang Yuantian address space defined by its parent bus, and resource zero 37eaf76b21STang Yuantian represents the clock register set 38eaf76b21STang Yuantian- clock-frequency: Input system clock frequency 39eaf76b21STang Yuantian 40eaf76b21STang YuantianRecommended properties: 41eaf76b21STang Yuantian- ranges: Allows valid translation between child's address space and 42eaf76b21STang Yuantian parent's. Must be present if the device has sub-nodes. 43eaf76b21STang Yuantian- #address-cells: Specifies the number of cells used to represent 44eaf76b21STang Yuantian physical base addresses. Must be present if the device has 45eaf76b21STang Yuantian sub-nodes and set to 1 if present 46eaf76b21STang Yuantian- #size-cells: Specifies the number of cells used to represent 47eaf76b21STang Yuantian the size of an address. Must be present if the device has 48eaf76b21STang Yuantian sub-nodes and set to 1 if present 49eaf76b21STang Yuantian 50eaf76b21STang Yuantian2. Clock Provider/Consumer Binding 51eaf76b21STang Yuantian 52eaf76b21STang YuantianMost of the bindings are from the common clock binding[1]. 53eaf76b21STang Yuantian [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 54eaf76b21STang Yuantian 55eaf76b21STang YuantianRequired properties: 56eaf76b21STang Yuantian- compatible : Should include one of the following: 57eaf76b21STang Yuantian * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) 58eaf76b21STang Yuantian * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) 59eaf76b21STang Yuantian * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) 60eaf76b21STang Yuantian * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) 61eaf76b21STang Yuantian * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). 62eaf76b21STang Yuantian It takes parent's clock-frequency as its clock. 63eaf76b21STang Yuantian * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). 64eaf76b21STang Yuantian It takes parent's clock-frequency as its clock. 65f1aa77c9SEmil Medve * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) 66f1aa77c9SEmil Medve * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) 67eaf76b21STang Yuantian- #clock-cells: From common clock binding. The number of cells in a 68eaf76b21STang Yuantian clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" 69eaf76b21STang Yuantian clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. 70eaf76b21STang Yuantian For "fsl,qoriq-core-pll-[1,2].0" clocks, the single 71eaf76b21STang Yuantian clock-specifier cell may take the following values: 72eaf76b21STang Yuantian * 0 - equal to the PLL frequency 73eaf76b21STang Yuantian * 1 - equal to the PLL frequency divided by 2 74eaf76b21STang Yuantian * 2 - equal to the PLL frequency divided by 4 75eaf76b21STang Yuantian 76eaf76b21STang YuantianRecommended properties: 77eaf76b21STang Yuantian- clocks: Should be the phandle of input parent clock 78eaf76b21STang Yuantian- clock-names: From common clock binding, indicates the clock name 79eaf76b21STang Yuantian- clock-output-names: From common clock binding, indicates the names of 80eaf76b21STang Yuantian output clocks 81eaf76b21STang Yuantian- reg: Should be the offset and length of clock block base address. 82eaf76b21STang Yuantian The length should be 4. 83eaf76b21STang Yuantian 84eaf76b21STang YuantianExample for clock block and clock provider: 85eaf76b21STang Yuantian/ { 86eaf76b21STang Yuantian clockgen: global-utilities@e1000 { 87eaf76b21STang Yuantian compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 88eaf76b21STang Yuantian ranges = <0x0 0xe1000 0x1000>; 89eaf76b21STang Yuantian clock-frequency = <133333333>; 90eaf76b21STang Yuantian reg = <0xe1000 0x1000>; 91eaf76b21STang Yuantian #address-cells = <1>; 92eaf76b21STang Yuantian #size-cells = <1>; 93eaf76b21STang Yuantian 94eaf76b21STang Yuantian sysclk: sysclk { 95eaf76b21STang Yuantian #clock-cells = <0>; 96eaf76b21STang Yuantian compatible = "fsl,qoriq-sysclk-1.0"; 97eaf76b21STang Yuantian clock-output-names = "sysclk"; 98eaf76b21STang Yuantian }; 99eaf76b21STang Yuantian 100eaf76b21STang Yuantian pll0: pll0@800 { 101eaf76b21STang Yuantian #clock-cells = <1>; 102eaf76b21STang Yuantian reg = <0x800 0x4>; 103eaf76b21STang Yuantian compatible = "fsl,qoriq-core-pll-1.0"; 104eaf76b21STang Yuantian clocks = <&sysclk>; 105eaf76b21STang Yuantian clock-output-names = "pll0", "pll0-div2"; 106eaf76b21STang Yuantian }; 107eaf76b21STang Yuantian 108eaf76b21STang Yuantian pll1: pll1@820 { 109eaf76b21STang Yuantian #clock-cells = <1>; 110eaf76b21STang Yuantian reg = <0x820 0x4>; 111eaf76b21STang Yuantian compatible = "fsl,qoriq-core-pll-1.0"; 112eaf76b21STang Yuantian clocks = <&sysclk>; 113eaf76b21STang Yuantian clock-output-names = "pll1", "pll1-div2"; 114eaf76b21STang Yuantian }; 115eaf76b21STang Yuantian 116eaf76b21STang Yuantian mux0: mux0@0 { 117eaf76b21STang Yuantian #clock-cells = <0>; 118eaf76b21STang Yuantian reg = <0x0 0x4>; 119eaf76b21STang Yuantian compatible = "fsl,qoriq-core-mux-1.0"; 120eaf76b21STang Yuantian clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 121eaf76b21STang Yuantian clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 122eaf76b21STang Yuantian clock-output-names = "cmux0"; 123eaf76b21STang Yuantian }; 124eaf76b21STang Yuantian 125eaf76b21STang Yuantian mux1: mux1@20 { 126eaf76b21STang Yuantian #clock-cells = <0>; 127eaf76b21STang Yuantian reg = <0x20 0x4>; 128eaf76b21STang Yuantian compatible = "fsl,qoriq-core-mux-1.0"; 129eaf76b21STang Yuantian clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 130eaf76b21STang Yuantian clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 131eaf76b21STang Yuantian clock-output-names = "cmux1"; 132eaf76b21STang Yuantian }; 133f1aa77c9SEmil Medve 134f1aa77c9SEmil Medve platform-pll: platform-pll@c00 { 135f1aa77c9SEmil Medve #clock-cells = <1>; 136f1aa77c9SEmil Medve reg = <0xc00 0x4>; 137f1aa77c9SEmil Medve compatible = "fsl,qoriq-platform-pll-1.0"; 138f1aa77c9SEmil Medve clocks = <&sysclk>; 139f1aa77c9SEmil Medve clock-output-names = "platform-pll", "platform-pll-div2"; 140eaf76b21STang Yuantian }; 141f1aa77c9SEmil Medve }; 142f1aa77c9SEmil Medve}; 143eaf76b21STang Yuantian 144eaf76b21STang YuantianExample for clock consumer: 145eaf76b21STang Yuantian 146eaf76b21STang Yuantian/ { 147eaf76b21STang Yuantian cpu0: PowerPC,e5500@0 { 148eaf76b21STang Yuantian ... 149eaf76b21STang Yuantian clocks = <&mux0>; 150eaf76b21STang Yuantian ... 151eaf76b21STang Yuantian }; 152f1aa77c9SEmil Medve}; 153