193a17c05STang Yuantian* Clock Block on Freescale QorIQ Platforms 2eaf76b21STang Yuantian 30dfc86b3SScott WoodFreescale QorIQ chips take primary clocking input from the external 4eaf76b21STang YuantianSYSCLK signal. The SYSCLK input (frequency) is multiplied using 5eaf76b21STang Yuantianmultiple phase locked loops (PLL) to create a variety of frequencies 6eaf76b21STang Yuantianwhich can then be passed to a variety of internal logic, including 7eaf76b21STang Yuantiancores and peripheral IP blocks. 8eaf76b21STang YuantianPlease refer to the Reference Manual for details. 9eaf76b21STang Yuantian 10eaf76b21STang YuantianAll references to "1.0" and "2.0" refer to the QorIQ chassis version to 11eaf76b21STang Yuantianwhich the chip complies. 12eaf76b21STang Yuantian 13eaf76b21STang YuantianChassis Version Example Chips 14eaf76b21STang Yuantian--------------- ------------- 15eaf76b21STang Yuantian1.0 p4080, p5020, p5040 160dfc86b3SScott Wood2.0 t4240, b4860 17eaf76b21STang Yuantian 18eaf76b21STang Yuantian1. Clock Block Binding 19eaf76b21STang Yuantian 20eaf76b21STang YuantianRequired properties: 210dfc86b3SScott Wood- compatible: Should contain a chip-specific clock block compatible 220dfc86b3SScott Wood string and (if applicable) may contain a chassis-version clock 230dfc86b3SScott Wood compatible string. 240dfc86b3SScott Wood 250dfc86b3SScott Wood Chip-specific strings are of the form "fsl,<chip>-clockgen", such as: 26eaf76b21STang Yuantian * "fsl,p2041-clockgen" 27eaf76b21STang Yuantian * "fsl,p3041-clockgen" 28eaf76b21STang Yuantian * "fsl,p4080-clockgen" 29eaf76b21STang Yuantian * "fsl,p5020-clockgen" 30eaf76b21STang Yuantian * "fsl,p5040-clockgen" 31eaf76b21STang Yuantian * "fsl,t4240-clockgen" 32eaf76b21STang Yuantian * "fsl,b4420-clockgen" 33eaf76b21STang Yuantian * "fsl,b4860-clockgen" 3473447f68SHarninder Rai * "fsl,ls1012a-clockgen" 3593a17c05STang Yuantian * "fsl,ls1021a-clockgen" 362b688d5bSShaohui Xie * "fsl,ls1043a-clockgen" 372b688d5bSShaohui Xie * "fsl,ls1046a-clockgen" 38124248e2SHarninder Rai * "fsl,ls1088a-clockgen" 392b688d5bSShaohui Xie * "fsl,ls2080a-clockgen" 400dfc86b3SScott Wood Chassis-version clock strings include: 41eaf76b21STang Yuantian * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks 42eaf76b21STang Yuantian * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks 43eaf76b21STang Yuantian- reg: Describes the address of the device's resources within the 44eaf76b21STang Yuantian address space defined by its parent bus, and resource zero 45eaf76b21STang Yuantian represents the clock register set 46eaf76b21STang Yuantian 470dfc86b3SScott WoodOptional properties: 48eaf76b21STang Yuantian- ranges: Allows valid translation between child's address space and 49eaf76b21STang Yuantian parent's. Must be present if the device has sub-nodes. 50eaf76b21STang Yuantian- #address-cells: Specifies the number of cells used to represent 51eaf76b21STang Yuantian physical base addresses. Must be present if the device has 52eaf76b21STang Yuantian sub-nodes and set to 1 if present 53eaf76b21STang Yuantian- #size-cells: Specifies the number of cells used to represent 54eaf76b21STang Yuantian the size of an address. Must be present if the device has 55eaf76b21STang Yuantian sub-nodes and set to 1 if present 560dfc86b3SScott Wood- clock-frequency: Input system clock frequency (SYSCLK) 570dfc86b3SScott Wood- clocks: If clock-frequency is not specified, sysclk may be provided 580dfc86b3SScott Wood as an input clock. Either clock-frequency or clocks must be 590dfc86b3SScott Wood provided. 60eaf76b21STang Yuantian 610dfc86b3SScott Wood2. Clock Provider 620dfc86b3SScott Wood 630dfc86b3SScott WoodThe clockgen node should act as a clock provider, though in older device 640dfc86b3SScott Woodtrees the children of the clockgen node are the clock providers. 650dfc86b3SScott Wood 660dfc86b3SScott WoodWhen the clockgen node is a clock provider, #clock-cells = <2>. 670dfc86b3SScott WoodThe first cell of the clock specifier is the clock type, and the 680dfc86b3SScott Woodsecond cell is the clock index for the specified type. 690dfc86b3SScott Wood 700dfc86b3SScott Wood Type# Name Index Cell 710dfc86b3SScott Wood 0 sysclk must be 0 720dfc86b3SScott Wood 1 cmux index (n in CLKCnCSR) 730dfc86b3SScott Wood 2 hwaccel index (n in CLKCGnHWACSR) 740dfc86b3SScott Wood 3 fman 0 for fm1, 1 for fm2 750dfc86b3SScott Wood 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 760dfc86b3SScott Wood 770dfc86b3SScott Wood3. Example 780dfc86b3SScott Wood 790dfc86b3SScott Wood clockgen: global-utilities@e1000 { 800dfc86b3SScott Wood compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 810dfc86b3SScott Wood clock-frequency = <133333333>; 820dfc86b3SScott Wood reg = <0xe1000 0x1000>; 830dfc86b3SScott Wood #clock-cells = <2>; 840dfc86b3SScott Wood }; 850dfc86b3SScott Wood 860dfc86b3SScott Wood fman@400000 { 870dfc86b3SScott Wood ... 880dfc86b3SScott Wood clocks = <&clockgen 3 0>; 890dfc86b3SScott Wood ... 900dfc86b3SScott Wood }; 910dfc86b3SScott Wood} 920dfc86b3SScott Wood4. Legacy Child Nodes 930dfc86b3SScott Wood 940dfc86b3SScott WoodNOTE: These nodes are deprecated. Kernels should continue to support 950dfc86b3SScott Wooddevice trees with these nodes, but new device trees should not use them. 96eaf76b21STang Yuantian 97eaf76b21STang YuantianMost of the bindings are from the common clock binding[1]. 98eaf76b21STang Yuantian [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 99eaf76b21STang Yuantian 100eaf76b21STang YuantianRequired properties: 101eaf76b21STang Yuantian- compatible : Should include one of the following: 102eaf76b21STang Yuantian * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) 103eaf76b21STang Yuantian * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) 104eaf76b21STang Yuantian * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) 105eaf76b21STang Yuantian * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) 106eaf76b21STang Yuantian * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). 107eaf76b21STang Yuantian It takes parent's clock-frequency as its clock. 108eaf76b21STang Yuantian * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). 109eaf76b21STang Yuantian It takes parent's clock-frequency as its clock. 110f1aa77c9SEmil Medve * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) 111f1aa77c9SEmil Medve * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) 112eaf76b21STang Yuantian- #clock-cells: From common clock binding. The number of cells in a 113eaf76b21STang Yuantian clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" 114eaf76b21STang Yuantian clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. 115eaf76b21STang Yuantian For "fsl,qoriq-core-pll-[1,2].0" clocks, the single 116eaf76b21STang Yuantian clock-specifier cell may take the following values: 117eaf76b21STang Yuantian * 0 - equal to the PLL frequency 118eaf76b21STang Yuantian * 1 - equal to the PLL frequency divided by 2 119eaf76b21STang Yuantian * 2 - equal to the PLL frequency divided by 4 120eaf76b21STang Yuantian 121eaf76b21STang YuantianRecommended properties: 122eaf76b21STang Yuantian- clocks: Should be the phandle of input parent clock 123eaf76b21STang Yuantian- clock-names: From common clock binding, indicates the clock name 124eaf76b21STang Yuantian- clock-output-names: From common clock binding, indicates the names of 125eaf76b21STang Yuantian output clocks 126eaf76b21STang Yuantian- reg: Should be the offset and length of clock block base address. 127eaf76b21STang Yuantian The length should be 4. 128eaf76b21STang Yuantian 1290dfc86b3SScott WoodLegacy Example: 130eaf76b21STang Yuantian/ { 131eaf76b21STang Yuantian clockgen: global-utilities@e1000 { 132eaf76b21STang Yuantian compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 133eaf76b21STang Yuantian ranges = <0x0 0xe1000 0x1000>; 134eaf76b21STang Yuantian clock-frequency = <133333333>; 135eaf76b21STang Yuantian reg = <0xe1000 0x1000>; 136eaf76b21STang Yuantian #address-cells = <1>; 137eaf76b21STang Yuantian #size-cells = <1>; 138eaf76b21STang Yuantian 139eaf76b21STang Yuantian sysclk: sysclk { 140eaf76b21STang Yuantian #clock-cells = <0>; 141eaf76b21STang Yuantian compatible = "fsl,qoriq-sysclk-1.0"; 142eaf76b21STang Yuantian clock-output-names = "sysclk"; 143eaf76b21STang Yuantian }; 144eaf76b21STang Yuantian 145eaf76b21STang Yuantian pll0: pll0@800 { 146eaf76b21STang Yuantian #clock-cells = <1>; 147eaf76b21STang Yuantian reg = <0x800 0x4>; 148eaf76b21STang Yuantian compatible = "fsl,qoriq-core-pll-1.0"; 149eaf76b21STang Yuantian clocks = <&sysclk>; 150eaf76b21STang Yuantian clock-output-names = "pll0", "pll0-div2"; 151eaf76b21STang Yuantian }; 152eaf76b21STang Yuantian 153eaf76b21STang Yuantian pll1: pll1@820 { 154eaf76b21STang Yuantian #clock-cells = <1>; 155eaf76b21STang Yuantian reg = <0x820 0x4>; 156eaf76b21STang Yuantian compatible = "fsl,qoriq-core-pll-1.0"; 157eaf76b21STang Yuantian clocks = <&sysclk>; 158eaf76b21STang Yuantian clock-output-names = "pll1", "pll1-div2"; 159eaf76b21STang Yuantian }; 160eaf76b21STang Yuantian 161eaf76b21STang Yuantian mux0: mux0@0 { 162eaf76b21STang Yuantian #clock-cells = <0>; 163eaf76b21STang Yuantian reg = <0x0 0x4>; 164eaf76b21STang Yuantian compatible = "fsl,qoriq-core-mux-1.0"; 165eaf76b21STang Yuantian clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 166eaf76b21STang Yuantian clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 167eaf76b21STang Yuantian clock-output-names = "cmux0"; 168eaf76b21STang Yuantian }; 169eaf76b21STang Yuantian 170eaf76b21STang Yuantian mux1: mux1@20 { 171eaf76b21STang Yuantian #clock-cells = <0>; 172eaf76b21STang Yuantian reg = <0x20 0x4>; 173eaf76b21STang Yuantian compatible = "fsl,qoriq-core-mux-1.0"; 174eaf76b21STang Yuantian clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 175eaf76b21STang Yuantian clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 176eaf76b21STang Yuantian clock-output-names = "cmux1"; 177eaf76b21STang Yuantian }; 178f1aa77c9SEmil Medve 179f1aa77c9SEmil Medve platform-pll: platform-pll@c00 { 180f1aa77c9SEmil Medve #clock-cells = <1>; 181f1aa77c9SEmil Medve reg = <0xc00 0x4>; 182f1aa77c9SEmil Medve compatible = "fsl,qoriq-platform-pll-1.0"; 183f1aa77c9SEmil Medve clocks = <&sysclk>; 184f1aa77c9SEmil Medve clock-output-names = "platform-pll", "platform-pll-div2"; 185eaf76b21STang Yuantian }; 186f1aa77c9SEmil Medve }; 187f1aa77c9SEmil Medve}; 188eaf76b21STang Yuantian 1890dfc86b3SScott WoodExample for legacy clock consumer: 190eaf76b21STang Yuantian 191eaf76b21STang Yuantian/ { 192eaf76b21STang Yuantian cpu0: PowerPC,e5500@0 { 193eaf76b21STang Yuantian ... 194eaf76b21STang Yuantian clocks = <&mux0>; 195eaf76b21STang Yuantian ... 196eaf76b21STang Yuantian }; 197f1aa77c9SEmil Medve}; 198