1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Video Clock & Reset Controller on SM8450
8
9maintainers:
10  - Taniya Das <quic_tdas@quicinc.com>
11
12description: |
13  Qualcomm video clock control module provides the clocks, resets and power
14  domains on SM8450.
15
16  See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
17
18properties:
19  compatible:
20    const: qcom,sm8450-videocc
21
22  reg:
23    maxItems: 1
24
25  clocks:
26    items:
27      - description: Board XO source
28      - description: Video AHB clock from GCC
29
30  power-domains:
31    maxItems: 1
32    description:
33      MMCX power domain.
34
35  required-opps:
36    maxItems: 1
37    description:
38      A phandle to an OPP node describing required MMCX performance point.
39
40  '#clock-cells':
41    const: 1
42
43  '#reset-cells':
44    const: 1
45
46  '#power-domain-cells':
47    const: 1
48
49required:
50  - compatible
51  - reg
52  - clocks
53  - power-domains
54  - required-opps
55  - '#clock-cells'
56  - '#reset-cells'
57  - '#power-domain-cells'
58
59additionalProperties: false
60
61examples:
62  - |
63    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
64    #include <dt-bindings/clock/qcom,rpmh.h>
65    #include <dt-bindings/power/qcom-rpmpd.h>
66    videocc: clock-controller@aaf0000 {
67      compatible = "qcom,sm8450-videocc";
68      reg = <0x0aaf0000 0x10000>;
69      clocks = <&rpmhcc RPMH_CXO_CLK>,
70               <&gcc GCC_VIDEO_AHB_CLK>;
71      power-domains = <&rpmhpd SM8450_MMCX>;
72      required-opps = <&rpmhpd_opp_low_svs>;
73      #clock-cells = <1>;
74      #reset-cells = <1>;
75      #power-domain-cells = <1>;
76    };
77...
78