1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Multimedia Clock & Reset Controller
8
9maintainers:
10  - Jeffrey Hugo <quic_jhugo@quicinc.com>
11  - Taniya Das <tdas@codeaurora.org>
12
13description: |
14  Qualcomm multimedia clock control module provides the clocks, resets and
15  power domains.
16
17properties:
18  compatible:
19    enum:
20      - qcom,mmcc-apq8064
21      - qcom,mmcc-apq8084
22      - qcom,mmcc-msm8226
23      - qcom,mmcc-msm8660
24      - qcom,mmcc-msm8960
25      - qcom,mmcc-msm8974
26      - qcom,mmcc-msm8992
27      - qcom,mmcc-msm8994
28      - qcom,mmcc-msm8996
29      - qcom,mmcc-msm8998
30      - qcom,mmcc-sdm630
31      - qcom,mmcc-sdm660
32
33  clocks:
34    minItems: 8
35    maxItems: 10
36
37  clock-names:
38    minItems: 8
39    maxItems: 10
40
41  '#clock-cells':
42    const: 1
43
44  '#reset-cells':
45    const: 1
46
47  '#power-domain-cells':
48    const: 1
49
50  reg:
51    maxItems: 1
52
53  protected-clocks:
54    description:
55      Protected clock specifier list as per common clock binding
56
57  vdd-gfx-supply:
58    description:
59      Regulator supply for the GPU_GX GDSC
60
61required:
62  - compatible
63  - reg
64  - '#clock-cells'
65  - '#reset-cells'
66  - '#power-domain-cells'
67
68additionalProperties: false
69
70allOf:
71  - if:
72      properties:
73        compatible:
74          contains:
75            enum:
76              - qcom,mmcc-apq8064
77              - qcom,mmcc-msm8960
78    then:
79      properties:
80        clocks:
81          items:
82            - description: Board PXO source
83            - description: PLL 3 clock
84            - description: PLL 3 Vote clock
85            - description: DSI phy instance 1 dsi clock
86            - description: DSI phy instance 1 byte clock
87            - description: DSI phy instance 2 dsi clock
88            - description: DSI phy instance 2 byte clock
89            - description: HDMI phy PLL clock
90
91        clock-names:
92          items:
93            - const: pxo
94            - const: pll3
95            - const: pll8_vote
96            - const: dsi1pll
97            - const: dsi1pllbyte
98            - const: dsi2pll
99            - const: dsi2pllbyte
100            - const: hdmipll
101
102  - if:
103      properties:
104        compatible:
105          contains:
106            enum:
107              - qcom,mmcc-msm8974
108    then:
109      properties:
110        clocks:
111          items:
112            - description: Board XO source
113            - description: MMSS GPLL0 voted clock
114            - description: GPLL0 voted clock
115            - description: GPLL1 voted clock
116            - description: GFX3D clock source
117            - description: DSI phy instance 0 dsi clock
118            - description: DSI phy instance 0 byte clock
119            - description: DSI phy instance 1 dsi clock
120            - description: DSI phy instance 1 byte clock
121            - description: HDMI phy PLL clock
122            - description: eDP phy PLL link clock
123            - description: eDP phy PLL vco clock
124
125        clock-names:
126          items:
127            - const: xo
128            - const: mmss_gpll0_vote
129            - const: gpll0_vote
130            - const: gpll1_vote
131            - const: gfx3d_clk_src
132            - const: dsi0pll
133            - const: dsi0pllbyte
134            - const: dsi1pll
135            - const: dsi1pllbyte
136            - const: hdmipll
137            - const: edp_link_clk
138            - const: edp_vco_div
139
140  - if:
141      properties:
142        compatible:
143          contains:
144            enum:
145              - qcom,mmcc-msm8994
146              - qcom,mmcc-msm8998
147              - qcom,mmcc-sdm630
148              - qcom,mmcc-sdm660
149    then:
150      required:
151        - clocks
152        - clock-names
153
154  - if:
155      properties:
156        compatible:
157          contains:
158            const: qcom,mmcc-msm8994
159    then:
160      properties:
161        clocks:
162          items:
163            - description: Board XO source
164            - description: Global PLL 0 clock
165            - description: MMSS NoC AHB clock
166            - description: GFX3D clock
167            - description: DSI phy instance 0 dsi clock
168            - description: DSI phy instance 0 byte clock
169            - description: DSI phy instance 1 dsi clock
170            - description: DSI phy instance 1 byte clock
171            - description: HDMI phy PLL clock
172
173        clock-names:
174          items:
175            - const: xo
176            - const: gpll0
177            - const: mmssnoc_ahb
178            - const: oxili_gfx3d_clk_src
179            - const: dsi0pll
180            - const: dsi0pllbyte
181            - const: dsi1pll
182            - const: dsi1pllbyte
183            - const: hdmipll
184
185  - if:
186      properties:
187        compatible:
188          contains:
189            const: qcom,mmcc-msm8996
190    then:
191      properties:
192        clocks:
193          items:
194            - description: Board XO source
195            - description: Global PLL 0 clock
196            - description: MMSS NoC AHB clock
197            - description: DSI phy instance 0 dsi clock
198            - description: DSI phy instance 0 byte clock
199            - description: DSI phy instance 1 dsi clock
200            - description: DSI phy instance 1 byte clock
201            - description: HDMI phy PLL clock
202
203        clock-names:
204          items:
205            - const: xo
206            - const: gpll0
207            - const: gcc_mmss_noc_cfg_ahb_clk
208            - const: dsi0pll
209            - const: dsi0pllbyte
210            - const: dsi1pll
211            - const: dsi1pllbyte
212            - const: hdmipll
213
214  - if:
215      properties:
216        compatible:
217          contains:
218            const: qcom,mmcc-msm8998
219    then:
220      properties:
221        clocks:
222          items:
223            - description: Board XO source
224            - description: Global PLL 0 clock
225            - description: DSI phy instance 0 dsi clock
226            - description: DSI phy instance 0 byte clock
227            - description: DSI phy instance 1 dsi clock
228            - description: DSI phy instance 1 byte clock
229            - description: HDMI phy PLL clock
230            - description: DisplayPort phy PLL link clock
231            - description: DisplayPort phy PLL vco clock
232            - description: Test clock
233
234        clock-names:
235          items:
236            - const: xo
237            - const: gpll0
238            - const: dsi0dsi
239            - const: dsi0byte
240            - const: dsi1dsi
241            - const: dsi1byte
242            - const: hdmipll
243            - const: dplink
244            - const: dpvco
245            - const: core_bi_pll_test_se
246
247  - if:
248      properties:
249        compatible:
250          contains:
251            enum:
252              - qcom,mmcc-sdm630
253              - qcom,mmcc-sdm660
254    then:
255      properties:
256        clocks:
257          items:
258            - description: Board XO source
259            - description: Board sleep source
260            - description: Global PLL 0 clock
261            - description: Global PLL 0 DIV clock
262            - description: DSI phy instance 0 dsi clock
263            - description: DSI phy instance 0 byte clock
264            - description: DSI phy instance 1 dsi clock
265            - description: DSI phy instance 1 byte clock
266            - description: DisplayPort phy PLL link clock
267            - description: DisplayPort phy PLL vco clock
268
269        clock-names:
270          items:
271            - const: xo
272            - const: sleep_clk
273            - const: gpll0
274            - const: gpll0_div
275            - const: dsi0pll
276            - const: dsi0pllbyte
277            - const: dsi1pll
278            - const: dsi1pllbyte
279            - const: dp_link_2x_clk_divsel_five
280            - const: dp_vco_divided_clk_src_mux
281
282examples:
283  # Example for MMCC for MSM8960:
284  - |
285    clock-controller@4000000 {
286      compatible = "qcom,mmcc-msm8960";
287      reg = <0x4000000 0x1000>;
288      #clock-cells = <1>;
289      #reset-cells = <1>;
290      #power-domain-cells = <1>;
291    };
292...
293