1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,lcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm LPASS Clock & Reset Controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12properties:
13  compatible:
14    enum:
15      - qcom,lcc-apq8064
16      - qcom,lcc-ipq8064
17      - qcom,lcc-mdm9615
18      - qcom,lcc-msm8960
19
20  clocks:
21    maxItems: 8
22
23  clock-names:
24    maxItems: 8
25
26  '#clock-cells':
27    const: 1
28
29  '#reset-cells':
30    const: 1
31
32  reg:
33    maxItems: 1
34
35required:
36  - compatible
37  - reg
38  - '#clock-cells'
39  - '#reset-cells'
40
41additionalProperties: false
42
43allOf:
44  - if:
45      properties:
46        compatible:
47          contains:
48            enum:
49              - qcom,lcc-apq8064
50              - qcom,lcc-msm8960
51    then:
52      properties:
53        clocks:
54          items:
55            - description: Board PXO source
56            - description: PLL 4 Vote clock
57            - description: MI2S codec clock
58            - description: Mic I2S codec clock
59            - description: Mic I2S spare clock
60            - description: Speaker I2S codec clock
61            - description: Speaker I2S spare clock
62            - description: PCM codec clock
63
64        clock-names:
65          items:
66            - const: pxo
67            - const: pll4_vote
68            - const: mi2s_codec_clk
69            - const: codec_i2s_mic_codec_clk
70            - const: spare_i2s_mic_codec_clk
71            - const: codec_i2s_spkr_codec_clk
72            - const: spare_i2s_spkr_codec_clk
73            - const: pcm_codec_clk
74
75      required:
76        - clocks
77        - clock-names
78
79examples:
80  - |
81    clock-controller@28000000 {
82        compatible = "qcom,lcc-ipq8064";
83        reg = <0x28000000 0x1000>;
84        #clock-cells = <1>;
85        #reset-cells = <1>;
86    };
87