1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller Binding
8
9maintainers:
10  - Taniya Das <tdas@codeaurora.org>
11
12description: |
13  Qualcomm graphics clock control module which supports the clocks, resets and
14  power domains on Qualcomm SoCs.
15
16  See also:
17    dt-bindings/clock/qcom,gpucc-sdm845.h
18    dt-bindings/clock/qcom,gpucc-sc7180.h
19    dt-bindings/clock/qcom,gpucc-sc7280.h
20    dt-bindings/clock/qcom,gpucc-sc8280xp.h
21    dt-bindings/clock/qcom,gpucc-sm6350.h
22    dt-bindings/clock/qcom,gpucc-sm8150.h
23    dt-bindings/clock/qcom,gpucc-sm8250.h
24
25properties:
26  compatible:
27    enum:
28      - qcom,sdm845-gpucc
29      - qcom,sc7180-gpucc
30      - qcom,sc7280-gpucc
31      - qcom,sc8180x-gpucc
32      - qcom,sc8280xp-gpucc
33      - qcom,sm6350-gpucc
34      - qcom,sm8150-gpucc
35      - qcom,sm8250-gpucc
36
37  clocks:
38    items:
39      - description: Board XO source
40      - description: GPLL0 main branch source
41      - description: GPLL0 div branch source
42
43  clock-names:
44    items:
45      - const: bi_tcxo
46      - const: gcc_gpu_gpll0_clk_src
47      - const: gcc_gpu_gpll0_div_clk_src
48
49  '#clock-cells':
50    const: 1
51
52  '#reset-cells':
53    const: 1
54
55  '#power-domain-cells':
56    const: 1
57
58  reg:
59    maxItems: 1
60
61required:
62  - compatible
63  - reg
64  - clocks
65  - clock-names
66  - '#clock-cells'
67  - '#reset-cells'
68  - '#power-domain-cells'
69
70additionalProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
75    #include <dt-bindings/clock/qcom,rpmh.h>
76    clock-controller@5090000 {
77      compatible = "qcom,sdm845-gpucc";
78      reg = <0x05090000 0x9000>;
79      clocks = <&rpmhcc RPMH_CXO_CLK>,
80               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
81               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
82      clock-names = "bi_tcxo",
83                    "gcc_gpu_gpll0_clk_src",
84                    "gcc_gpu_gpll0_div_clk_src";
85      #clock-cells = <1>;
86      #reset-cells = <1>;
87      #power-domain-cells = <1>;
88    };
89...
90