1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Graphics Clock & Reset Controller Binding 8 9maintainers: 10 - Taniya Das <tdas@codeaurora.org> 11 12description: | 13 Qualcomm graphics clock control module which supports the clocks, resets and 14 power domains on Qualcomm SoCs. 15 16 See also: 17 dt-bindings/clock/qcom,gpucc-sdm845.h 18 dt-bindings/clock/qcom,gpucc-sc7180.h 19 dt-bindings/clock/qcom,gpucc-sc7280.h 20 dt-bindings/clock/qcom,gpucc-sm8150.h 21 dt-bindings/clock/qcom,gpucc-sm8250.h 22 23properties: 24 compatible: 25 enum: 26 - qcom,sdm845-gpucc 27 - qcom,sc7180-gpucc 28 - qcom,sc7280-gpucc 29 - qcom,sc8180x-gpucc 30 - qcom,sm8150-gpucc 31 - qcom,sm8250-gpucc 32 33 clocks: 34 items: 35 - description: Board XO source 36 - description: GPLL0 main branch source 37 - description: GPLL0 div branch source 38 39 clock-names: 40 items: 41 - const: bi_tcxo 42 - const: gcc_gpu_gpll0_clk_src 43 - const: gcc_gpu_gpll0_div_clk_src 44 45 '#clock-cells': 46 const: 1 47 48 '#reset-cells': 49 const: 1 50 51 '#power-domain-cells': 52 const: 1 53 54 reg: 55 maxItems: 1 56 57required: 58 - compatible 59 - reg 60 - clocks 61 - clock-names 62 - '#clock-cells' 63 - '#reset-cells' 64 - '#power-domain-cells' 65 66additionalProperties: false 67 68examples: 69 - | 70 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 71 #include <dt-bindings/clock/qcom,rpmh.h> 72 clock-controller@5090000 { 73 compatible = "qcom,sdm845-gpucc"; 74 reg = <0x05090000 0x9000>; 75 clocks = <&rpmhcc RPMH_CXO_CLK>, 76 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 77 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 78 clock-names = "bi_tcxo", 79 "gcc_gpu_gpll0_clk_src", 80 "gcc_gpu_gpll0_div_clk_src"; 81 #clock-cells = <1>; 82 #reset-cells = <1>; 83 #power-domain-cells = <1>; 84 }; 85... 86