1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller Binding
8
9maintainers:
10  - Taniya Das <tdas@codeaurora.org>
11
12description: |
13  Qualcomm graphics clock control module which supports the clocks, resets and
14  power domains on SDM845/SC7180/SM8150/SM8250.
15
16  See also:
17    dt-bindings/clock/qcom,gpucc-sdm845.h
18    dt-bindings/clock/qcom,gpucc-sc7180.h
19    dt-bindings/clock/qcom,gpucc-sm8150.h
20    dt-bindings/clock/qcom,gpucc-sm8250.h
21
22properties:
23  compatible:
24    enum:
25      - qcom,sdm845-gpucc
26      - qcom,sc7180-gpucc
27      - qcom,sm8150-gpucc
28      - qcom,sm8250-gpucc
29
30  clocks:
31    items:
32      - description: Board XO source
33      - description: GPLL0 main branch source
34      - description: GPLL0 div branch source
35
36  clock-names:
37    items:
38      - const: bi_tcxo
39      - const: gcc_gpu_gpll0_clk_src
40      - const: gcc_gpu_gpll0_div_clk_src
41
42  '#clock-cells':
43    const: 1
44
45  '#reset-cells':
46    const: 1
47
48  '#power-domain-cells':
49    const: 1
50
51  reg:
52    maxItems: 1
53
54required:
55  - compatible
56  - reg
57  - clocks
58  - clock-names
59  - '#clock-cells'
60  - '#reset-cells'
61  - '#power-domain-cells'
62
63additionalProperties: false
64
65examples:
66  - |
67    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
68    #include <dt-bindings/clock/qcom,rpmh.h>
69    clock-controller@5090000 {
70      compatible = "qcom,sdm845-gpucc";
71      reg = <0x05090000 0x9000>;
72      clocks = <&rpmhcc RPMH_CXO_CLK>,
73               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
74               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
75      clock-names = "bi_tcxo",
76                    "gcc_gpu_gpll0_clk_src",
77                    "gcc_gpu_gpll0_div_clk_src";
78      #clock-cells = <1>;
79      #reset-cells = <1>;
80      #power-domain-cells = <1>;
81    };
82...
83