1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on SDX65
8
9maintainers:
10  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on SDX65
15
16  See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
17
18properties:
19  compatible:
20    const: qcom,gcc-sdx65
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Board active XO source
26      - description: Sleep clock source
27      - description: PCIE Pipe clock source
28      - description: USB3 phy wrapper pipe clock source
29      - description: PLL test clock source (Optional clock)
30    minItems: 5
31
32  clock-names:
33    items:
34      - const: bi_tcxo
35      - const: bi_tcxo_ao
36      - const: sleep_clk
37      - const: pcie_pipe_clk
38      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
39      - const: core_bi_pll_test_se # Optional clock
40    minItems: 5
41
42required:
43  - compatible
44  - clocks
45  - clock-names
46
47allOf:
48  - $ref: qcom,gcc.yaml#
49
50unevaluatedProperties: false
51
52examples:
53  - |
54    #include <dt-bindings/clock/qcom,rpmh.h>
55    clock-controller@100000 {
56      compatible = "qcom,gcc-sdx65";
57      reg = <0x100000 0x1f7400>;
58      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
59               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
60      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
61                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
62      #clock-cells = <1>;
63      #reset-cells = <1>;
64      #power-domain-cells = <1>;
65    };
66...
67