1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller Binding for SDX55
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description: |
14  Qualcomm global clock control module which supports the clocks, resets and
15  power domains on SDX55
16
17  See also:
18  - dt-bindings/clock/qcom,gcc-sdx55.h
19
20properties:
21  compatible:
22    const: qcom,gcc-sdx55
23
24  clocks:
25    items:
26      - description: Board XO source
27      - description: Sleep clock source
28      - description: PLL test clock source (Optional clock)
29    minItems: 2
30
31  clock-names:
32    items:
33      - const: bi_tcxo
34      - const: sleep_clk
35      - const: core_bi_pll_test_se # Optional clock
36    minItems: 2
37
38required:
39  - compatible
40  - clocks
41  - clock-names
42
43allOf:
44  - $ref: qcom,gcc.yaml#
45
46unevaluatedProperties: false
47
48examples:
49  - |
50    #include <dt-bindings/clock/qcom,rpmh.h>
51    clock-controller@100000 {
52      compatible = "qcom,gcc-sdx55";
53      reg = <0x00100000 0x1f0000>;
54      clocks = <&rpmhcc RPMH_CXO_CLK>,
55               <&sleep_clk>, <&pll_test_clk>;
56      clock-names = "bi_tcxo", "sleep_clk", "core_bi_pll_test_se";
57      #clock-cells = <1>;
58      #reset-cells = <1>;
59      #power-domain-cells = <1>;
60    };
61
62...
63