1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller Binding
8
9maintainers:
10  - Stephen Boyd <sboyd@kernel.org>
11  - Taniya Das <tdas@codeaurora.org>
12
13description: |
14  Qualcomm global clock control module which supports the clocks, resets and
15  power domains on SDM845
16
17  See also:
18  - dt-bindings/clock/qcom,gcc-sdm845.h
19
20properties:
21  compatible:
22    const: qcom,gcc-sdm845
23
24  clocks:
25    items:
26      - description: Board XO source
27      - description: Board active XO source
28      - description: Sleep clock source
29      - description: PCIE 0 Pipe clock source
30      - description: PCIE 1 Pipe clock source
31
32  clock-names:
33    items:
34      - const: bi_tcxo
35      - const: bi_tcxo_ao
36      - const: sleep_clk
37      - const: pcie_0_pipe_clk
38      - const: pcie_1_pipe_clk
39
40  '#clock-cells':
41    const: 1
42
43  '#reset-cells':
44    const: 1
45
46  '#power-domain-cells':
47    const: 1
48
49  reg:
50    maxItems: 1
51
52  protected-clocks:
53    description:
54      Protected clock specifier list as per common clock binding.
55
56required:
57  - compatible
58  - reg
59  - '#clock-cells'
60  - '#reset-cells'
61  - '#power-domain-cells'
62
63additionalProperties: false
64
65examples:
66  # Example for GCC for SDM845:
67  - |
68    #include <dt-bindings/clock/qcom,rpmh.h>
69    clock-controller@100000 {
70      compatible = "qcom,gcc-sdm845";
71      reg = <0x100000 0x1f0000>;
72      clocks = <&rpmhcc RPMH_CXO_CLK>,
73               <&rpmhcc RPMH_CXO_CLK_A>,
74               <&sleep_clk>,
75               <&pcie0_lane>,
76               <&pcie1_lane>;
77      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
78      #clock-cells = <1>;
79      #reset-cells = <1>;
80      #power-domain-cells = <1>;
81    };
82...
83