1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845
8
9maintainers:
10  - Stephen Boyd <sboyd@kernel.org>
11  - Taniya Das <quic_tdas@quicinc.com>
12
13description: |
14  Qualcomm global clock control module provides the clocks, resets and power
15  domains on SDM670 and SDM845
16
17  See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
18
19properties:
20  compatible:
21    enum:
22      - qcom,gcc-sdm670
23      - qcom,gcc-sdm845
24
25  clocks:
26    minItems: 3
27    maxItems: 5
28
29  clock-names:
30    minItems: 3
31    maxItems: 5
32
33  power-domains:
34    maxItems: 1
35
36required:
37  - compatible
38
39allOf:
40  - $ref: qcom,gcc.yaml#
41  - if:
42      properties:
43        compatible:
44          contains:
45            const: qcom,gcc-sdm670
46    then:
47      properties:
48        clocks:
49          items:
50            - description: Board XO source
51            - description: Board active XO source
52            - description: Sleep clock source
53        clock-names:
54          items:
55            - const: bi_tcxo
56            - const: bi_tcxo_ao
57            - const: sleep_clk
58
59  - if:
60      properties:
61        compatible:
62          contains:
63            const: qcom,gcc-sdm845
64    then:
65      properties:
66        clocks:
67          items:
68            - description: Board XO source
69            - description: Board active XO source
70            - description: Sleep clock source
71            - description: PCIE 0 Pipe clock source
72            - description: PCIE 1 Pipe clock source
73        clock-names:
74          items:
75            - const: bi_tcxo
76            - const: bi_tcxo_ao
77            - const: sleep_clk
78            - const: pcie_0_pipe_clk
79            - const: pcie_1_pipe_clk
80
81unevaluatedProperties: false
82
83examples:
84  # Example for GCC for SDM845:
85  - |
86    #include <dt-bindings/clock/qcom,rpmh.h>
87    clock-controller@100000 {
88      compatible = "qcom,gcc-sdm845";
89      reg = <0x100000 0x1f0000>;
90      clocks = <&rpmhcc RPMH_CXO_CLK>,
91               <&rpmhcc RPMH_CXO_CLK_A>,
92               <&sleep_clk>,
93               <&pcie0_lane>,
94               <&pcie1_lane>;
95      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
96      #clock-cells = <1>;
97      #reset-cells = <1>;
98      #power-domain-cells = <1>;
99    };
100...
101