1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Qualcomm global clock control module which supports the clocks, resets and
14  power domains on SC8280xp.
15
16  See also:
17  - include/dt-bindings/clock/qcom,gcc-sc8280xp.h
18
19properties:
20  compatible:
21    const: qcom,gcc-sc8280xp
22
23  clocks:
24    items:
25      - description: XO reference clock
26      - description: Sleep clock
27      - description: UFS memory first RX symbol clock
28      - description: UFS memory second RX symbol clock
29      - description: UFS memory first TX symbol clock
30      - description: UFS card first RX symbol clock
31      - description: UFS card second RX symbol clock
32      - description: UFS card first TX symbol clock
33      - description: Primary USB SuperSpeed pipe clock
34      - description: USB4 PHY pipegmux clock source
35      - description: USB4 PHY DP gmux clock source
36      - description: USB4 PHY sys pipegmux clock source
37      - description: USB4 PHY PCIe pipe clock
38      - description: USB4 PHY router max pipe clock
39      - description: Primary USB4 RX0 clock
40      - description: Primary USB4 RX1 clock
41      - description: Secondary USB SuperSpeed pipe clock
42      - description: Second USB4 PHY pipegmux clock source
43      - description: Second USB4 PHY DP gmux clock source
44      - description: Second USB4 PHY sys pipegmux clock source
45      - description: Second USB4 PHY PCIe pipe clock
46      - description: Second USB4 PHY router max pipe clock
47      - description: Secondary USB4 RX0 clock
48      - description: Secondary USB4 RX1 clock
49      - description: Multiport USB first SuperSpeed pipe clock
50      - description: Multiport USB second SuperSpeed pipe clock
51      - description: PCIe 2a pipe clock
52      - description: PCIe 2b pipe clock
53      - description: PCIe 3a pipe clock
54      - description: PCIe 3b pipe clock
55      - description: PCIe 4 pipe clock
56      - description: First EMAC controller reference clock
57      - description: Second EMAC controller reference clock
58
59  protected-clocks:
60    maxItems: 389
61
62required:
63  - compatible
64  - clocks
65
66allOf:
67  - $ref: qcom,gcc.yaml#
68
69unevaluatedProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/clock/qcom,rpmh.h>
74    clock-controller@100000 {
75      compatible = "qcom,gcc-sc8280xp";
76      reg = <0x00100000 0x1f0000>;
77      clocks = <&rpmhcc RPMH_CXO_CLK>,
78               <&sleep_clk>,
79               <&ufs_phy_rx_symbol_0_clk>,
80               <&ufs_phy_rx_symbol_1_clk>,
81               <&ufs_phy_tx_symbol_0_clk>,
82               <&ufs_card_rx_symbol_0_clk>,
83               <&ufs_card_rx_symbol_1_clk>,
84               <&ufs_card_tx_symbol_0_clk>,
85               <&usb_0_ssphy>,
86               <&gcc_usb4_phy_pipegmux_clk_src>,
87               <&gcc_usb4_phy_dp_gmux_clk_src>,
88               <&gcc_usb4_phy_sys_pipegmux_clk_src>,
89               <&usb4_phy_gcc_usb4_pcie_pipe_clk>,
90               <&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
91               <&qusb4phy_gcc_usb4_rx0_clk>,
92               <&qusb4phy_gcc_usb4_rx1_clk>,
93               <&usb_1_ssphy>,
94               <&gcc_usb4_1_phy_pipegmux_clk_src>,
95               <&gcc_usb4_1_phy_dp_gmux_clk_src>,
96               <&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
97               <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
98               <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
99               <&qusb4phy_1_gcc_usb4_rx0_clk>,
100               <&qusb4phy_1_gcc_usb4_rx1_clk>,
101               <&usb_2_ssphy>,
102               <&usb_3_ssphy>,
103               <&pcie2a_lane>,
104               <&pcie2b_lane>,
105               <&pcie3a_lane>,
106               <&pcie3b_lane>,
107               <&pcie4_lane>,
108               <&rxc0_ref_clk>,
109               <&rxc1_ref_clk>;
110
111      #clock-cells = <1>;
112      #reset-cells = <1>;
113      #power-domain-cells = <1>;
114    };
115...
116