163f4e4b6SKonrad Dybcio# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 263f4e4b6SKonrad Dybcio%YAML 1.2 363f4e4b6SKonrad Dybcio--- 463f4e4b6SKonrad Dybcio$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml# 563f4e4b6SKonrad Dybcio$schema: http://devicetree.org/meta-schemas/core.yaml# 663f4e4b6SKonrad Dybcio 763f4e4b6SKonrad Dybciotitle: Qualcomm Graphics Clock & Reset Controller on SM8450 863f4e4b6SKonrad Dybcio 963f4e4b6SKonrad Dybciomaintainers: 1063f4e4b6SKonrad Dybcio - Konrad Dybcio <konrad.dybcio@linaro.org> 1163f4e4b6SKonrad Dybcio 1263f4e4b6SKonrad Dybciodescription: | 1363f4e4b6SKonrad Dybcio Qualcomm graphics clock control module provides the clocks, resets and power 1463f4e4b6SKonrad Dybcio domains on Qualcomm SoCs. 1563f4e4b6SKonrad Dybcio 1663f4e4b6SKonrad Dybcio See also:: 1763f4e4b6SKonrad Dybcio include/dt-bindings/clock/qcom,sm8450-gpucc.h 18*778af143SJagadeesh Kona include/dt-bindings/clock/qcom,sm8550-gpucc.h 1963f4e4b6SKonrad Dybcio include/dt-bindings/reset/qcom,sm8450-gpucc.h 2063f4e4b6SKonrad Dybcio 2163f4e4b6SKonrad Dybcioproperties: 2263f4e4b6SKonrad Dybcio compatible: 2363f4e4b6SKonrad Dybcio enum: 2463f4e4b6SKonrad Dybcio - qcom,sm8450-gpucc 25*778af143SJagadeesh Kona - qcom,sm8550-gpucc 2663f4e4b6SKonrad Dybcio 2763f4e4b6SKonrad Dybcio clocks: 2863f4e4b6SKonrad Dybcio items: 2963f4e4b6SKonrad Dybcio - description: Board XO source 3063f4e4b6SKonrad Dybcio - description: GPLL0 main branch source 3163f4e4b6SKonrad Dybcio - description: GPLL0 div branch source 3263f4e4b6SKonrad Dybcio 3363f4e4b6SKonrad Dybcio '#clock-cells': 3463f4e4b6SKonrad Dybcio const: 1 3563f4e4b6SKonrad Dybcio 3663f4e4b6SKonrad Dybcio '#reset-cells': 3763f4e4b6SKonrad Dybcio const: 1 3863f4e4b6SKonrad Dybcio 3963f4e4b6SKonrad Dybcio '#power-domain-cells': 4063f4e4b6SKonrad Dybcio const: 1 4163f4e4b6SKonrad Dybcio 4263f4e4b6SKonrad Dybcio reg: 4363f4e4b6SKonrad Dybcio maxItems: 1 4463f4e4b6SKonrad Dybcio 4563f4e4b6SKonrad Dybciorequired: 4663f4e4b6SKonrad Dybcio - compatible 4763f4e4b6SKonrad Dybcio - reg 4863f4e4b6SKonrad Dybcio - clocks 4963f4e4b6SKonrad Dybcio - '#clock-cells' 5063f4e4b6SKonrad Dybcio - '#reset-cells' 5163f4e4b6SKonrad Dybcio - '#power-domain-cells' 5263f4e4b6SKonrad Dybcio 5363f4e4b6SKonrad DybcioadditionalProperties: false 5463f4e4b6SKonrad Dybcio 5563f4e4b6SKonrad Dybcioexamples: 5663f4e4b6SKonrad Dybcio - | 5763f4e4b6SKonrad Dybcio #include <dt-bindings/clock/qcom,gcc-sm8450.h> 5863f4e4b6SKonrad Dybcio #include <dt-bindings/clock/qcom,rpmh.h> 5963f4e4b6SKonrad Dybcio 6063f4e4b6SKonrad Dybcio soc { 6163f4e4b6SKonrad Dybcio #address-cells = <2>; 6263f4e4b6SKonrad Dybcio #size-cells = <2>; 6363f4e4b6SKonrad Dybcio 6463f4e4b6SKonrad Dybcio clock-controller@3d90000 { 6563f4e4b6SKonrad Dybcio compatible = "qcom,sm8450-gpucc"; 6663f4e4b6SKonrad Dybcio reg = <0 0x03d90000 0 0xa000>; 6763f4e4b6SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 6863f4e4b6SKonrad Dybcio <&gcc GCC_GPU_GPLL0_CLK_SRC>, 6963f4e4b6SKonrad Dybcio <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 7063f4e4b6SKonrad Dybcio #clock-cells = <1>; 7163f4e4b6SKonrad Dybcio #reset-cells = <1>; 7263f4e4b6SKonrad Dybcio #power-domain-cells = <1>; 7363f4e4b6SKonrad Dybcio }; 7463f4e4b6SKonrad Dybcio }; 7563f4e4b6SKonrad Dybcio... 76