148cabc22SDouglas Anderson# SPDX-License-Identifier: GPL-2.0-only 248cabc22SDouglas Anderson%YAML 1.2 348cabc22SDouglas Anderson--- 448cabc22SDouglas Anderson$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml# 548cabc22SDouglas Anderson$schema: http://devicetree.org/meta-schemas/core.yaml# 648cabc22SDouglas Anderson 748cabc22SDouglas Andersontitle: Qualcomm Display Clock & Reset Controller Binding for SDM845 848cabc22SDouglas Anderson 948cabc22SDouglas Andersonmaintainers: 1048cabc22SDouglas Anderson - Taniya Das <tdas@codeaurora.org> 1148cabc22SDouglas Anderson 1248cabc22SDouglas Andersondescription: | 1348cabc22SDouglas Anderson Qualcomm display clock control module which supports the clocks, resets and 1448cabc22SDouglas Anderson power domains on SDM845. 1548cabc22SDouglas Anderson 1648cabc22SDouglas Anderson See also dt-bindings/clock/qcom,dispcc-sdm845.h. 1748cabc22SDouglas Anderson 1848cabc22SDouglas Andersonproperties: 1948cabc22SDouglas Anderson compatible: 2048cabc22SDouglas Anderson const: qcom,sdm845-dispcc 2148cabc22SDouglas Anderson 2248cabc22SDouglas Anderson # NOTE: sdm845.dtsi existed for quite some time and specified no clocks. 2348cabc22SDouglas Anderson # The code had to use hardcoded mechanisms to find the input clocks. 2448cabc22SDouglas Anderson # New dts files should have these clocks. 2548cabc22SDouglas Anderson clocks: 2648cabc22SDouglas Anderson items: 2748cabc22SDouglas Anderson - description: Board XO source 2848cabc22SDouglas Anderson - description: GPLL0 source from GCC 2948cabc22SDouglas Anderson - description: GPLL0 div source from GCC 3048cabc22SDouglas Anderson - description: Byte clock from DSI PHY0 3148cabc22SDouglas Anderson - description: Pixel clock from DSI PHY0 3248cabc22SDouglas Anderson - description: Byte clock from DSI PHY1 3348cabc22SDouglas Anderson - description: Pixel clock from DSI PHY1 3448cabc22SDouglas Anderson - description: Link clock from DP PHY 3548cabc22SDouglas Anderson - description: VCO DIV clock from DP PHY 3648cabc22SDouglas Anderson 3748cabc22SDouglas Anderson clock-names: 3848cabc22SDouglas Anderson items: 3948cabc22SDouglas Anderson - const: bi_tcxo 4048cabc22SDouglas Anderson - const: gcc_disp_gpll0_clk_src 4148cabc22SDouglas Anderson - const: gcc_disp_gpll0_div_clk_src 4248cabc22SDouglas Anderson - const: dsi0_phy_pll_out_byteclk 4348cabc22SDouglas Anderson - const: dsi0_phy_pll_out_dsiclk 4448cabc22SDouglas Anderson - const: dsi1_phy_pll_out_byteclk 4548cabc22SDouglas Anderson - const: dsi1_phy_pll_out_dsiclk 4648cabc22SDouglas Anderson - const: dp_link_clk_divsel_ten 4748cabc22SDouglas Anderson - const: dp_vco_divided_clk_src_mux 4848cabc22SDouglas Anderson 4948cabc22SDouglas Anderson '#clock-cells': 5048cabc22SDouglas Anderson const: 1 5148cabc22SDouglas Anderson 5248cabc22SDouglas Anderson '#reset-cells': 5348cabc22SDouglas Anderson const: 1 5448cabc22SDouglas Anderson 5548cabc22SDouglas Anderson '#power-domain-cells': 5648cabc22SDouglas Anderson const: 1 5748cabc22SDouglas Anderson 5848cabc22SDouglas Anderson reg: 5948cabc22SDouglas Anderson maxItems: 1 6048cabc22SDouglas Anderson 6148cabc22SDouglas Andersonrequired: 6248cabc22SDouglas Anderson - compatible 6348cabc22SDouglas Anderson - reg 6448cabc22SDouglas Anderson - clocks 6548cabc22SDouglas Anderson - clock-names 6648cabc22SDouglas Anderson - '#clock-cells' 6748cabc22SDouglas Anderson - '#reset-cells' 6848cabc22SDouglas Anderson - '#power-domain-cells' 6948cabc22SDouglas Anderson 707f464532SRob HerringadditionalProperties: false 717f464532SRob Herring 7248cabc22SDouglas Andersonexamples: 7348cabc22SDouglas Anderson - | 7448cabc22SDouglas Anderson #include <dt-bindings/clock/qcom,gcc-sdm845.h> 7548cabc22SDouglas Anderson #include <dt-bindings/clock/qcom,rpmh.h> 7648cabc22SDouglas Anderson clock-controller@af00000 { 7748cabc22SDouglas Anderson compatible = "qcom,sdm845-dispcc"; 7848cabc22SDouglas Anderson reg = <0 0x0af00000 0 0x10000>; 7948cabc22SDouglas Anderson clocks = <&rpmhcc RPMH_CXO_CLK>, 8048cabc22SDouglas Anderson <&gcc GCC_DISP_GPLL0_CLK_SRC>, 8148cabc22SDouglas Anderson <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 8248cabc22SDouglas Anderson <&dsi0_phy 0>, 8348cabc22SDouglas Anderson <&dsi0_phy 1>, 8448cabc22SDouglas Anderson <&dsi1_phy 0>, 8548cabc22SDouglas Anderson <&dsi1_phy 1>, 8648cabc22SDouglas Anderson <&dp_phy 0>, 8748cabc22SDouglas Anderson <&dp_phy 1>; 8848cabc22SDouglas Anderson clock-names = "bi_tcxo", 8948cabc22SDouglas Anderson "gcc_disp_gpll0_clk_src", 9048cabc22SDouglas Anderson "gcc_disp_gpll0_div_clk_src", 9148cabc22SDouglas Anderson "dsi0_phy_pll_out_byteclk", 9248cabc22SDouglas Anderson "dsi0_phy_pll_out_dsiclk", 9348cabc22SDouglas Anderson "dsi1_phy_pll_out_byteclk", 9448cabc22SDouglas Anderson "dsi1_phy_pll_out_dsiclk", 9548cabc22SDouglas Anderson "dp_link_clk_divsel_ten", 9648cabc22SDouglas Anderson "dp_vco_divided_clk_src_mux"; 9748cabc22SDouglas Anderson #clock-cells = <1>; 9848cabc22SDouglas Anderson #reset-cells = <1>; 9948cabc22SDouglas Anderson #power-domain-cells = <1>; 10048cabc22SDouglas Anderson }; 10148cabc22SDouglas Anderson... 102