148cabc22SDouglas Anderson# SPDX-License-Identifier: GPL-2.0-only 248cabc22SDouglas Anderson%YAML 1.2 348cabc22SDouglas Anderson--- 448cabc22SDouglas Anderson$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml# 548cabc22SDouglas Anderson$schema: http://devicetree.org/meta-schemas/core.yaml# 648cabc22SDouglas Anderson 748cabc22SDouglas Andersontitle: Qualcomm Display Clock & Reset Controller Binding for SC7180 848cabc22SDouglas Anderson 948cabc22SDouglas Andersonmaintainers: 1048cabc22SDouglas Anderson - Taniya Das <tdas@codeaurora.org> 1148cabc22SDouglas Anderson 1248cabc22SDouglas Andersondescription: | 1348cabc22SDouglas Anderson Qualcomm display clock control module which supports the clocks, resets and 1448cabc22SDouglas Anderson power domains on SC7180. 1548cabc22SDouglas Anderson 1648cabc22SDouglas Anderson See also dt-bindings/clock/qcom,dispcc-sc7180.h. 1748cabc22SDouglas Anderson 1848cabc22SDouglas Andersonproperties: 1948cabc22SDouglas Anderson compatible: 2048cabc22SDouglas Anderson const: qcom,sc7180-dispcc 2148cabc22SDouglas Anderson 2248cabc22SDouglas Anderson clocks: 2348cabc22SDouglas Anderson items: 2448cabc22SDouglas Anderson - description: Board XO source 2548cabc22SDouglas Anderson - description: GPLL0 source from GCC 2648cabc22SDouglas Anderson - description: Byte clock from DSI PHY 2748cabc22SDouglas Anderson - description: Pixel clock from DSI PHY 2848cabc22SDouglas Anderson - description: Link clock from DP PHY 2948cabc22SDouglas Anderson - description: VCO DIV clock from DP PHY 3048cabc22SDouglas Anderson 3148cabc22SDouglas Anderson clock-names: 3248cabc22SDouglas Anderson items: 3348cabc22SDouglas Anderson - const: bi_tcxo 3448cabc22SDouglas Anderson - const: gcc_disp_gpll0_clk_src 3548cabc22SDouglas Anderson - const: dsi0_phy_pll_out_byteclk 3648cabc22SDouglas Anderson - const: dsi0_phy_pll_out_dsiclk 3748cabc22SDouglas Anderson - const: dp_phy_pll_link_clk 3848cabc22SDouglas Anderson - const: dp_phy_pll_vco_div_clk 3948cabc22SDouglas Anderson 4048cabc22SDouglas Anderson '#clock-cells': 4148cabc22SDouglas Anderson const: 1 4248cabc22SDouglas Anderson 4348cabc22SDouglas Anderson '#reset-cells': 4448cabc22SDouglas Anderson const: 1 4548cabc22SDouglas Anderson 4648cabc22SDouglas Anderson '#power-domain-cells': 4748cabc22SDouglas Anderson const: 1 4848cabc22SDouglas Anderson 4948cabc22SDouglas Anderson reg: 5048cabc22SDouglas Anderson maxItems: 1 5148cabc22SDouglas Anderson 5248cabc22SDouglas Andersonrequired: 5348cabc22SDouglas Anderson - compatible 5448cabc22SDouglas Anderson - reg 5548cabc22SDouglas Anderson - clocks 5648cabc22SDouglas Anderson - clock-names 5748cabc22SDouglas Anderson - '#clock-cells' 5848cabc22SDouglas Anderson - '#reset-cells' 5948cabc22SDouglas Anderson - '#power-domain-cells' 6048cabc22SDouglas Anderson 6148cabc22SDouglas Andersonexamples: 6248cabc22SDouglas Anderson - | 6348cabc22SDouglas Anderson #include <dt-bindings/clock/qcom,gcc-sc7180.h> 6448cabc22SDouglas Anderson #include <dt-bindings/clock/qcom,rpmh.h> 6548cabc22SDouglas Anderson clock-controller@af00000 { 6648cabc22SDouglas Anderson compatible = "qcom,sc7180-dispcc"; 6748cabc22SDouglas Anderson reg = <0 0x0af00000 0 0x200000>; 6848cabc22SDouglas Anderson clocks = <&rpmhcc RPMH_CXO_CLK>, 6948cabc22SDouglas Anderson <&gcc GCC_DISP_GPLL0_CLK_SRC>, 7048cabc22SDouglas Anderson <&dsi_phy 0>, 7148cabc22SDouglas Anderson <&dsi_phy 1>, 7248cabc22SDouglas Anderson <&dp_phy 0>, 7348cabc22SDouglas Anderson <&dp_phy 1>; 7448cabc22SDouglas Anderson clock-names = "bi_tcxo", 7548cabc22SDouglas Anderson "gcc_disp_gpll0_clk_src", 7648cabc22SDouglas Anderson "dsi0_phy_pll_out_byteclk", 7748cabc22SDouglas Anderson "dsi0_phy_pll_out_dsiclk", 7848cabc22SDouglas Anderson "dp_phy_pll_link_clk", 7948cabc22SDouglas Anderson "dp_phy_pll_vco_div_clk"; 8048cabc22SDouglas Anderson #clock-cells = <1>; 8148cabc22SDouglas Anderson #reset-cells = <1>; 8248cabc22SDouglas Anderson #power-domain-cells = <1>; 8348cabc22SDouglas Anderson }; 8448cabc22SDouglas Anderson... 85