1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller Binding
8
9maintainers:
10  - Taniya Das <tdas@codeaurora.org>
11
12description: |
13  Qualcomm grpahics clock control module which supports the clocks, resets and
14  power domains.
15
16properties:
17  compatible:
18    enum:
19      - qcom,msm8998-gpucc
20      - qcom,sc7180-gpucc
21      - qcom,sdm845-gpucc
22
23  clocks:
24    minItems: 1
25    maxItems: 3
26    items:
27      - description: Board XO source
28      - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src)
29      - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src)
30
31  clock-names:
32    minItems: 1
33    maxItems: 3
34    items:
35      - const: xo
36      - const: gpll0_main
37      - const: gpll0_div
38
39  '#clock-cells':
40    const: 1
41
42  '#reset-cells':
43    const: 1
44
45  '#power-domain-cells':
46    const: 1
47
48  reg:
49    maxItems: 1
50
51required:
52  - compatible
53  - reg
54  - clocks
55  - clock-names
56  - '#clock-cells'
57  - '#reset-cells'
58  - '#power-domain-cells'
59
60examples:
61  # Example of GPUCC with clock node properties for SDM845:
62  - |
63    clock-controller@5090000 {
64      compatible = "qcom,sdm845-gpucc";
65      reg = <0x5090000 0x9000>;
66      clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>;
67      clock-names = "xo", "gpll0_main", "gpll0_div";
68      #clock-cells = <1>;
69      #reset-cells = <1>;
70      #power-domain-cells = <1>;
71     };
72...
73