1*2f9b2096SKrzysztof Kozlowski# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*2f9b2096SKrzysztof Kozlowski%YAML 1.2
3*2f9b2096SKrzysztof Kozlowski---
4*2f9b2096SKrzysztof Kozlowski$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
5*2f9b2096SKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml#
6*2f9b2096SKrzysztof Kozlowski
7*2f9b2096SKrzysztof Kozlowskititle: Qualcomm Global Clock & Reset Controller on MSM8953
8*2f9b2096SKrzysztof Kozlowski
9*2f9b2096SKrzysztof Kozlowskimaintainers:
10*2f9b2096SKrzysztof Kozlowski  - Adam Skladowski <a_skl39@protonmail.com>
11*2f9b2096SKrzysztof Kozlowski  - Sireesh Kodali <sireeshkodali@protonmail.com>
12*2f9b2096SKrzysztof Kozlowski
13*2f9b2096SKrzysztof Kozlowskidescription: |
14*2f9b2096SKrzysztof Kozlowski  Qualcomm global clock control module provides the clocks, resets and power
15*2f9b2096SKrzysztof Kozlowski  domains on MSM8953.
16*2f9b2096SKrzysztof Kozlowski
17*2f9b2096SKrzysztof Kozlowski  See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
18*2f9b2096SKrzysztof Kozlowski
19*2f9b2096SKrzysztof Kozlowskiproperties:
20*2f9b2096SKrzysztof Kozlowski  compatible:
21*2f9b2096SKrzysztof Kozlowski    const: qcom,gcc-msm8953
22*2f9b2096SKrzysztof Kozlowski
23*2f9b2096SKrzysztof Kozlowski  clocks:
24*2f9b2096SKrzysztof Kozlowski    items:
25*2f9b2096SKrzysztof Kozlowski      - description: Board XO source
26*2f9b2096SKrzysztof Kozlowski      - description: Sleep clock source
27*2f9b2096SKrzysztof Kozlowski      - description: Byte clock from DSI PHY0
28*2f9b2096SKrzysztof Kozlowski      - description: Pixel clock from DSI PHY0
29*2f9b2096SKrzysztof Kozlowski      - description: Byte clock from DSI PHY1
30*2f9b2096SKrzysztof Kozlowski      - description: Pixel clock from DSI PHY1
31*2f9b2096SKrzysztof Kozlowski
32*2f9b2096SKrzysztof Kozlowski  clock-names:
33*2f9b2096SKrzysztof Kozlowski    items:
34*2f9b2096SKrzysztof Kozlowski      - const: xo
35*2f9b2096SKrzysztof Kozlowski      - const: sleep
36*2f9b2096SKrzysztof Kozlowski      - const: dsi0pll
37*2f9b2096SKrzysztof Kozlowski      - const: dsi0pllbyte
38*2f9b2096SKrzysztof Kozlowski      - const: dsi1pll
39*2f9b2096SKrzysztof Kozlowski      - const: dsi1pllbyte
40*2f9b2096SKrzysztof Kozlowski
41*2f9b2096SKrzysztof Kozlowskirequired:
42*2f9b2096SKrzysztof Kozlowski  - compatible
43*2f9b2096SKrzysztof Kozlowski  - clocks
44*2f9b2096SKrzysztof Kozlowski  - clock-names
45*2f9b2096SKrzysztof Kozlowski
46*2f9b2096SKrzysztof KozlowskiallOf:
47*2f9b2096SKrzysztof Kozlowski  - $ref: qcom,gcc.yaml#
48*2f9b2096SKrzysztof Kozlowski
49*2f9b2096SKrzysztof KozlowskiunevaluatedProperties: false
50*2f9b2096SKrzysztof Kozlowski
51*2f9b2096SKrzysztof Kozlowskiexamples:
52*2f9b2096SKrzysztof Kozlowski  - |
53*2f9b2096SKrzysztof Kozlowski    #include <dt-bindings/clock/qcom,rpmcc.h>
54*2f9b2096SKrzysztof Kozlowski
55*2f9b2096SKrzysztof Kozlowski    clock-controller@1800000 {
56*2f9b2096SKrzysztof Kozlowski        compatible = "qcom,gcc-msm8953";
57*2f9b2096SKrzysztof Kozlowski        reg = <0x01800000 0x80000>;
58*2f9b2096SKrzysztof Kozlowski        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
59*2f9b2096SKrzysztof Kozlowski                 <&sleep_clk>,
60*2f9b2096SKrzysztof Kozlowski                 <&dsi0_phy 1>,
61*2f9b2096SKrzysztof Kozlowski                 <&dsi0_phy 0>,
62*2f9b2096SKrzysztof Kozlowski                 <&dsi1_phy 1>,
63*2f9b2096SKrzysztof Kozlowski                 <&dsi1_phy 0>;
64*2f9b2096SKrzysztof Kozlowski        clock-names = "xo",
65*2f9b2096SKrzysztof Kozlowski                      "sleep",
66*2f9b2096SKrzysztof Kozlowski                      "dsi0pll",
67*2f9b2096SKrzysztof Kozlowski                      "dsi0pllbyte",
68*2f9b2096SKrzysztof Kozlowski                      "dsi1pll",
69*2f9b2096SKrzysztof Kozlowski                      "dsi1pllbyte";
70*2f9b2096SKrzysztof Kozlowski        #clock-cells = <1>;
71*2f9b2096SKrzysztof Kozlowski        #reset-cells = <1>;
72*2f9b2096SKrzysztof Kozlowski        #power-domain-cells = <1>;
73*2f9b2096SKrzysztof Kozlowski    };
74