1*6914b82fSKonrad Dybcio# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*6914b82fSKonrad Dybcio%YAML 1.2 3*6914b82fSKonrad Dybcio--- 4*6914b82fSKonrad Dybcio$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml# 5*6914b82fSKonrad Dybcio$schema: http://devicetree.org/meta-schemas/core.yaml# 6*6914b82fSKonrad Dybcio 7*6914b82fSKonrad Dybciotitle: Qualcomm Display Clock & Reset Controller Binding for SM6350 8*6914b82fSKonrad Dybcio 9*6914b82fSKonrad Dybciomaintainers: 10*6914b82fSKonrad Dybcio - Konrad Dybcio <konrad.dybcio@somainline.org> 11*6914b82fSKonrad Dybcio 12*6914b82fSKonrad Dybciodescription: | 13*6914b82fSKonrad Dybcio Qualcomm display clock control module which supports the clocks, resets and 14*6914b82fSKonrad Dybcio power domains on SM6350. 15*6914b82fSKonrad Dybcio 16*6914b82fSKonrad Dybcio See also dt-bindings/clock/qcom,dispcc-sm6350.h. 17*6914b82fSKonrad Dybcio 18*6914b82fSKonrad Dybcioproperties: 19*6914b82fSKonrad Dybcio compatible: 20*6914b82fSKonrad Dybcio const: qcom,sm6350-dispcc 21*6914b82fSKonrad Dybcio 22*6914b82fSKonrad Dybcio clocks: 23*6914b82fSKonrad Dybcio items: 24*6914b82fSKonrad Dybcio - description: Board XO source 25*6914b82fSKonrad Dybcio - description: GPLL0 source from GCC 26*6914b82fSKonrad Dybcio - description: Byte clock from DSI PHY 27*6914b82fSKonrad Dybcio - description: Pixel clock from DSI PHY 28*6914b82fSKonrad Dybcio - description: Link clock from DP PHY 29*6914b82fSKonrad Dybcio - description: VCO DIV clock from DP PHY 30*6914b82fSKonrad Dybcio 31*6914b82fSKonrad Dybcio clock-names: 32*6914b82fSKonrad Dybcio items: 33*6914b82fSKonrad Dybcio - const: bi_tcxo 34*6914b82fSKonrad Dybcio - const: gcc_disp_gpll0_clk 35*6914b82fSKonrad Dybcio - const: dsi0_phy_pll_out_byteclk 36*6914b82fSKonrad Dybcio - const: dsi0_phy_pll_out_dsiclk 37*6914b82fSKonrad Dybcio - const: dp_phy_pll_link_clk 38*6914b82fSKonrad Dybcio - const: dp_phy_pll_vco_div_clk 39*6914b82fSKonrad Dybcio 40*6914b82fSKonrad Dybcio '#clock-cells': 41*6914b82fSKonrad Dybcio const: 1 42*6914b82fSKonrad Dybcio 43*6914b82fSKonrad Dybcio '#reset-cells': 44*6914b82fSKonrad Dybcio const: 1 45*6914b82fSKonrad Dybcio 46*6914b82fSKonrad Dybcio '#power-domain-cells': 47*6914b82fSKonrad Dybcio const: 1 48*6914b82fSKonrad Dybcio 49*6914b82fSKonrad Dybcio reg: 50*6914b82fSKonrad Dybcio maxItems: 1 51*6914b82fSKonrad Dybcio 52*6914b82fSKonrad Dybciorequired: 53*6914b82fSKonrad Dybcio - compatible 54*6914b82fSKonrad Dybcio - reg 55*6914b82fSKonrad Dybcio - clocks 56*6914b82fSKonrad Dybcio - clock-names 57*6914b82fSKonrad Dybcio - '#clock-cells' 58*6914b82fSKonrad Dybcio - '#reset-cells' 59*6914b82fSKonrad Dybcio - '#power-domain-cells' 60*6914b82fSKonrad Dybcio 61*6914b82fSKonrad DybcioadditionalProperties: false 62*6914b82fSKonrad Dybcio 63*6914b82fSKonrad Dybcioexamples: 64*6914b82fSKonrad Dybcio - | 65*6914b82fSKonrad Dybcio #include <dt-bindings/clock/qcom,gcc-sm6350.h> 66*6914b82fSKonrad Dybcio #include <dt-bindings/clock/qcom,rpmh.h> 67*6914b82fSKonrad Dybcio clock-controller@af00000 { 68*6914b82fSKonrad Dybcio compatible = "qcom,sm6350-dispcc"; 69*6914b82fSKonrad Dybcio reg = <0x0af00000 0x20000>; 70*6914b82fSKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 71*6914b82fSKonrad Dybcio <&gcc GCC_DISP_GPLL0_CLK>, 72*6914b82fSKonrad Dybcio <&dsi_phy 0>, 73*6914b82fSKonrad Dybcio <&dsi_phy 1>, 74*6914b82fSKonrad Dybcio <&dp_phy 0>, 75*6914b82fSKonrad Dybcio <&dp_phy 1>; 76*6914b82fSKonrad Dybcio clock-names = "bi_tcxo", 77*6914b82fSKonrad Dybcio "gcc_disp_gpll0_clk", 78*6914b82fSKonrad Dybcio "dsi0_phy_pll_out_byteclk", 79*6914b82fSKonrad Dybcio "dsi0_phy_pll_out_dsiclk", 80*6914b82fSKonrad Dybcio "dp_phy_pll_link_clk", 81*6914b82fSKonrad Dybcio "dp_phy_pll_vco_div_clk"; 82*6914b82fSKonrad Dybcio #clock-cells = <1>; 83*6914b82fSKonrad Dybcio #reset-cells = <1>; 84*6914b82fSKonrad Dybcio #power-domain-cells = <1>; 85*6914b82fSKonrad Dybcio }; 86*6914b82fSKonrad Dybcio... 87