16914b82fSKonrad Dybcio# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 26914b82fSKonrad Dybcio%YAML 1.2 36914b82fSKonrad Dybcio--- 46914b82fSKonrad Dybcio$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml# 56914b82fSKonrad Dybcio$schema: http://devicetree.org/meta-schemas/core.yaml# 66914b82fSKonrad Dybcio 7*ece3c319SKrzysztof Kozlowskititle: Qualcomm Display Clock & Reset Controller on SM6350 86914b82fSKonrad Dybcio 96914b82fSKonrad Dybciomaintainers: 106914b82fSKonrad Dybcio - Konrad Dybcio <konrad.dybcio@somainline.org> 116914b82fSKonrad Dybcio 126914b82fSKonrad Dybciodescription: | 13*ece3c319SKrzysztof Kozlowski Qualcomm display clock control module provides the clocks, resets and power 14*ece3c319SKrzysztof Kozlowski domains on SM6350. 156914b82fSKonrad Dybcio 16*ece3c319SKrzysztof Kozlowski See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h 176914b82fSKonrad Dybcio 186914b82fSKonrad Dybcioproperties: 196914b82fSKonrad Dybcio compatible: 206914b82fSKonrad Dybcio const: qcom,sm6350-dispcc 216914b82fSKonrad Dybcio 226914b82fSKonrad Dybcio clocks: 236914b82fSKonrad Dybcio items: 246914b82fSKonrad Dybcio - description: Board XO source 256914b82fSKonrad Dybcio - description: GPLL0 source from GCC 266914b82fSKonrad Dybcio - description: Byte clock from DSI PHY 276914b82fSKonrad Dybcio - description: Pixel clock from DSI PHY 286914b82fSKonrad Dybcio - description: Link clock from DP PHY 296914b82fSKonrad Dybcio - description: VCO DIV clock from DP PHY 306914b82fSKonrad Dybcio 316914b82fSKonrad Dybcio clock-names: 326914b82fSKonrad Dybcio items: 336914b82fSKonrad Dybcio - const: bi_tcxo 346914b82fSKonrad Dybcio - const: gcc_disp_gpll0_clk 356914b82fSKonrad Dybcio - const: dsi0_phy_pll_out_byteclk 366914b82fSKonrad Dybcio - const: dsi0_phy_pll_out_dsiclk 376914b82fSKonrad Dybcio - const: dp_phy_pll_link_clk 386914b82fSKonrad Dybcio - const: dp_phy_pll_vco_div_clk 396914b82fSKonrad Dybcio 406914b82fSKonrad Dybcio '#clock-cells': 416914b82fSKonrad Dybcio const: 1 426914b82fSKonrad Dybcio 436914b82fSKonrad Dybcio '#reset-cells': 446914b82fSKonrad Dybcio const: 1 456914b82fSKonrad Dybcio 466914b82fSKonrad Dybcio '#power-domain-cells': 476914b82fSKonrad Dybcio const: 1 486914b82fSKonrad Dybcio 496914b82fSKonrad Dybcio reg: 506914b82fSKonrad Dybcio maxItems: 1 516914b82fSKonrad Dybcio 526914b82fSKonrad Dybciorequired: 536914b82fSKonrad Dybcio - compatible 546914b82fSKonrad Dybcio - reg 556914b82fSKonrad Dybcio - clocks 566914b82fSKonrad Dybcio - clock-names 576914b82fSKonrad Dybcio - '#clock-cells' 586914b82fSKonrad Dybcio - '#reset-cells' 596914b82fSKonrad Dybcio - '#power-domain-cells' 606914b82fSKonrad Dybcio 616914b82fSKonrad DybcioadditionalProperties: false 626914b82fSKonrad Dybcio 636914b82fSKonrad Dybcioexamples: 646914b82fSKonrad Dybcio - | 656914b82fSKonrad Dybcio #include <dt-bindings/clock/qcom,gcc-sm6350.h> 666914b82fSKonrad Dybcio #include <dt-bindings/clock/qcom,rpmh.h> 676914b82fSKonrad Dybcio clock-controller@af00000 { 686914b82fSKonrad Dybcio compatible = "qcom,sm6350-dispcc"; 696914b82fSKonrad Dybcio reg = <0x0af00000 0x20000>; 706914b82fSKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 716914b82fSKonrad Dybcio <&gcc GCC_DISP_GPLL0_CLK>, 726914b82fSKonrad Dybcio <&dsi_phy 0>, 736914b82fSKonrad Dybcio <&dsi_phy 1>, 746914b82fSKonrad Dybcio <&dp_phy 0>, 756914b82fSKonrad Dybcio <&dp_phy 1>; 766914b82fSKonrad Dybcio clock-names = "bi_tcxo", 776914b82fSKonrad Dybcio "gcc_disp_gpll0_clk", 786914b82fSKonrad Dybcio "dsi0_phy_pll_out_byteclk", 796914b82fSKonrad Dybcio "dsi0_phy_pll_out_dsiclk", 806914b82fSKonrad Dybcio "dp_phy_pll_link_clk", 816914b82fSKonrad Dybcio "dp_phy_pll_vco_div_clk"; 826914b82fSKonrad Dybcio #clock-cells = <1>; 836914b82fSKonrad Dybcio #reset-cells = <1>; 846914b82fSKonrad Dybcio #power-domain-cells = <1>; 856914b82fSKonrad Dybcio }; 866914b82fSKonrad Dybcio... 87