1* Gated Clock bindings for Marvell Orion SoCs 2 3Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save 4some power. The clock consumer should specify the desired clock by having 5the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to 6the corresponding clock gating control bit in HW to ease manual clock lookup 7in datasheet. 8 9The following is a list of provided IDs for Armada 370: 10ID Clock Peripheral 11----------------------------------- 120 Audio AC97 Cntrl 131 pex0_en PCIe 0 Clock out 142 pex1_en PCIe 1 Clock out 153 ge1 Gigabit Ethernet 1 164 ge0 Gigabit Ethernet 0 175 pex0 PCIe Cntrl 0 189 pex1 PCIe Cntrl 1 1915 sata0 SATA Host 0 2017 sdio SDHCI Host 2125 tdm Time Division Mplx 2228 ddr DDR Cntrl 2330 sata1 SATA Host 0 24 25The following is a list of provided IDs for Armada XP: 26ID Clock Peripheral 27----------------------------------- 280 audio Audio Cntrl 291 ge3 Gigabit Ethernet 3 302 ge2 Gigabit Ethernet 2 313 ge1 Gigabit Ethernet 1 324 ge0 Gigabit Ethernet 0 335 pex0 PCIe Cntrl 0 346 pex1 PCIe Cntrl 1 357 pex2 PCIe Cntrl 2 368 pex3 PCIe Cntrl 3 3713 bp 3814 sata0lnk 3915 sata0 SATA Host 0 4016 lcd LCD Cntrl 4117 sdio SDHCI Host 4218 usb0 USB Host 0 4319 usb1 USB Host 1 4420 usb2 USB Host 2 4522 xor0 XOR DMA 0 4623 crypto CESA engine 4725 tdm Time Division Mplx 4828 xor1 XOR DMA 1 4929 sata1lnk 5030 sata1 SATA Host 0 51 52The following is a list of provided IDs for Dove: 53ID Clock Peripheral 54----------------------------------- 550 usb0 USB Host 0 561 usb1 USB Host 1 572 ge Gigabit Ethernet 583 sata SATA Host 594 pex0 PCIe Cntrl 0 605 pex1 PCIe Cntrl 1 618 sdio0 SDHCI Host 0 629 sdio1 SDHCI Host 1 6310 nand NAND Cntrl 6411 camera Camera Cntrl 6512 i2s0 I2S Cntrl 0 6613 i2s1 I2S Cntrl 1 6715 crypto CESA engine 6821 ac97 AC97 Cntrl 6922 pdma Peripheral DMA 7023 xor0 XOR DMA 0 7124 xor1 XOR DMA 1 7230 gephy Gigabit Ethernel PHY 73Note: gephy(30) is implemented as a parent clock of ge(2) 74 75The following is a list of provided IDs for Kirkwood: 76ID Clock Peripheral 77----------------------------------- 780 ge0 Gigabit Ethernet 0 792 pex0 PCIe Cntrl 0 803 usb0 USB Host 0 814 sdio SDIO Cntrl 825 tsu Transp. Stream Unit 836 dunit SDRAM Cntrl 847 runit Runit 858 xor0 XOR DMA 0 869 audio I2S Cntrl 0 8714 sata0 SATA Host 0 8815 sata1 SATA Host 1 8916 xor1 XOR DMA 1 9017 crypto CESA engine 9118 pex1 PCIe Cntrl 1 9219 ge1 Gigabit Ethernet 0 9320 tdm Time Division Mplx 94 95Required properties: 96- compatible : shall be one of the following: 97 "marvell,dove-gating-clock" - for Dove SoC clock gating 98 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating 99- reg : shall be the register address of the Clock Gating Control register 100- #clock-cells : from common clock binding; shall be set to 1 101 102Optional properties: 103- clocks : default parent clock phandle (e.g. tclk) 104 105Example: 106 107gate_clk: clock-gating-control@d0038 { 108 compatible = "marvell,dove-gating-clock"; 109 reg = <0xd0038 0x4>; 110 /* default parent clock is tclk */ 111 clocks = <&core_clk 0>; 112 #clock-cells = <1>; 113}; 114 115sdio0: sdio@92000 { 116 compatible = "marvell,dove-sdhci"; 117 /* get clk gate bit 8 (sdio0) */ 118 clocks = <&gate_clk 8>; 119}; 120