1*07300ef4SKavyasree Kotagiri# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*07300ef4SKavyasree Kotagiri%YAML 1.2 3*07300ef4SKavyasree Kotagiri--- 4*07300ef4SKavyasree Kotagiri$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml# 5*07300ef4SKavyasree Kotagiri$schema: http://devicetree.org/meta-schemas/core.yaml# 6*07300ef4SKavyasree Kotagiri 7*07300ef4SKavyasree Kotagirititle: Microchip LAN966X Generic Clock Controller 8*07300ef4SKavyasree Kotagiri 9*07300ef4SKavyasree Kotagirimaintainers: 10*07300ef4SKavyasree Kotagiri - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> 11*07300ef4SKavyasree Kotagiri 12*07300ef4SKavyasree Kotagiridescription: | 13*07300ef4SKavyasree Kotagiri The LAN966X Generic clock controller contains 3 PLLs - cpu_clk, 14*07300ef4SKavyasree Kotagiri ddr_clk and sys_clk. This clock controller generates and supplies 15*07300ef4SKavyasree Kotagiri clock to various peripherals within the SoC. 16*07300ef4SKavyasree Kotagiri 17*07300ef4SKavyasree Kotagiriproperties: 18*07300ef4SKavyasree Kotagiri compatible: 19*07300ef4SKavyasree Kotagiri const: microchip,lan966x-gck 20*07300ef4SKavyasree Kotagiri 21*07300ef4SKavyasree Kotagiri reg: 22*07300ef4SKavyasree Kotagiri maxItems: 1 23*07300ef4SKavyasree Kotagiri 24*07300ef4SKavyasree Kotagiri clocks: 25*07300ef4SKavyasree Kotagiri items: 26*07300ef4SKavyasree Kotagiri - description: CPU clock source 27*07300ef4SKavyasree Kotagiri - description: DDR clock source 28*07300ef4SKavyasree Kotagiri - description: System clock source 29*07300ef4SKavyasree Kotagiri 30*07300ef4SKavyasree Kotagiri clock-names: 31*07300ef4SKavyasree Kotagiri items: 32*07300ef4SKavyasree Kotagiri - const: cpu 33*07300ef4SKavyasree Kotagiri - const: ddr 34*07300ef4SKavyasree Kotagiri - const: sys 35*07300ef4SKavyasree Kotagiri 36*07300ef4SKavyasree Kotagiri '#clock-cells': 37*07300ef4SKavyasree Kotagiri const: 1 38*07300ef4SKavyasree Kotagiri 39*07300ef4SKavyasree Kotagirirequired: 40*07300ef4SKavyasree Kotagiri - compatible 41*07300ef4SKavyasree Kotagiri - reg 42*07300ef4SKavyasree Kotagiri - clocks 43*07300ef4SKavyasree Kotagiri - clock-names 44*07300ef4SKavyasree Kotagiri - '#clock-cells' 45*07300ef4SKavyasree Kotagiri 46*07300ef4SKavyasree KotagiriadditionalProperties: false 47*07300ef4SKavyasree Kotagiri 48*07300ef4SKavyasree Kotagiriexamples: 49*07300ef4SKavyasree Kotagiri - | 50*07300ef4SKavyasree Kotagiri clks: clock-controller@e00c00a8 { 51*07300ef4SKavyasree Kotagiri compatible = "microchip,lan966x-gck"; 52*07300ef4SKavyasree Kotagiri #clock-cells = <1>; 53*07300ef4SKavyasree Kotagiri clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; 54*07300ef4SKavyasree Kotagiri clock-names = "cpu", "ddr", "sys"; 55*07300ef4SKavyasree Kotagiri reg = <0xe00c00a8 0x38>; 56*07300ef4SKavyasree Kotagiri }; 57*07300ef4SKavyasree Kotagiri... 58