1cd9fdd06SYassine Oudjana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2cd9fdd06SYassine Oudjana%YAML 1.2 3cd9fdd06SYassine Oudjana--- 4cd9fdd06SYassine Oudjana$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#" 5cd9fdd06SYassine Oudjana$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6cd9fdd06SYassine Oudjana 7cd9fdd06SYassine Oudjanatitle: MediaTek Top Clock Generator Controller 8cd9fdd06SYassine Oudjana 9cd9fdd06SYassine Oudjanamaintainers: 10cd9fdd06SYassine Oudjana - Michael Turquette <mturquette@baylibre.com> 11cd9fdd06SYassine Oudjana - Stephen Boyd <sboyd@kernel.org> 12cd9fdd06SYassine Oudjana 13cd9fdd06SYassine Oudjanadescription: 14cd9fdd06SYassine Oudjana The Mediatek topckgen controller provides various clocks to the system. 15cd9fdd06SYassine Oudjana The clock values can be found in <dt-bindings/clock/mt*-clk.h>. 16cd9fdd06SYassine Oudjana 17cd9fdd06SYassine Oudjanaproperties: 18cd9fdd06SYassine Oudjana compatible: 19cd9fdd06SYassine Oudjana oneOf: 20cd9fdd06SYassine Oudjana - enum: 21cd9fdd06SYassine Oudjana - mediatek,mt6797-topckgen 22cd9fdd06SYassine Oudjana - mediatek,mt7622-topckgen 23cd9fdd06SYassine Oudjana - mediatek,mt8135-topckgen 24cd9fdd06SYassine Oudjana - mediatek,mt8173-topckgen 25cd9fdd06SYassine Oudjana - mediatek,mt8516-topckgen 26cd9fdd06SYassine Oudjana - items: 27cd9fdd06SYassine Oudjana - const: mediatek,mt7623-topckgen 28cd9fdd06SYassine Oudjana - const: mediatek,mt2701-topckgen 29cd9fdd06SYassine Oudjana - const: syscon 30cd9fdd06SYassine Oudjana - items: 31cd9fdd06SYassine Oudjana - enum: 32cd9fdd06SYassine Oudjana - mediatek,mt2701-topckgen 33cd9fdd06SYassine Oudjana - mediatek,mt2712-topckgen 34cd9fdd06SYassine Oudjana - mediatek,mt6765-topckgen 35cd9fdd06SYassine Oudjana - mediatek,mt6779-topckgen 36*d5099c95SAngeloGioacchino Del Regno - mediatek,mt6795-topckgen 37cd9fdd06SYassine Oudjana - mediatek,mt7629-topckgen 38cd9fdd06SYassine Oudjana - mediatek,mt7986-topckgen 39cd9fdd06SYassine Oudjana - mediatek,mt8167-topckgen 40cd9fdd06SYassine Oudjana - mediatek,mt8183-topckgen 41cd9fdd06SYassine Oudjana - const: syscon 42cd9fdd06SYassine Oudjana 43cd9fdd06SYassine Oudjana reg: 44cd9fdd06SYassine Oudjana maxItems: 1 45cd9fdd06SYassine Oudjana 46cd9fdd06SYassine Oudjana '#clock-cells': 47cd9fdd06SYassine Oudjana const: 1 48cd9fdd06SYassine Oudjana 49cd9fdd06SYassine Oudjanarequired: 50cd9fdd06SYassine Oudjana - compatible 51cd9fdd06SYassine Oudjana - reg 52cd9fdd06SYassine Oudjana - '#clock-cells' 53cd9fdd06SYassine Oudjana 54cd9fdd06SYassine OudjanaadditionalProperties: false 55cd9fdd06SYassine Oudjana 56cd9fdd06SYassine Oudjanaexamples: 57cd9fdd06SYassine Oudjana - | 58cd9fdd06SYassine Oudjana topckgen: clock-controller@10000000 { 59cd9fdd06SYassine Oudjana compatible = "mediatek,mt8173-topckgen"; 60cd9fdd06SYassine Oudjana reg = <0x10000000 0x1000>; 61cd9fdd06SYassine Oudjana #clock-cells = <1>; 62cd9fdd06SYassine Oudjana }; 63