1*1086a531SGarmin.Chang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*1086a531SGarmin.Chang%YAML 1.2 3*1086a531SGarmin.Chang--- 4*1086a531SGarmin.Chang$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml# 5*1086a531SGarmin.Chang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1086a531SGarmin.Chang 7*1086a531SGarmin.Changtitle: MediaTek System Clock Controller for MT8188 8*1086a531SGarmin.Chang 9*1086a531SGarmin.Changmaintainers: 10*1086a531SGarmin.Chang - Garmin Chang <garmin.chang@mediatek.com> 11*1086a531SGarmin.Chang 12*1086a531SGarmin.Changdescription: | 13*1086a531SGarmin.Chang The clock architecture in MediaTek like below 14*1086a531SGarmin.Chang PLLs --> 15*1086a531SGarmin.Chang dividers --> 16*1086a531SGarmin.Chang muxes 17*1086a531SGarmin.Chang --> 18*1086a531SGarmin.Chang clock gate 19*1086a531SGarmin.Chang 20*1086a531SGarmin.Chang The apmixedsys provides most of PLLs which generated from SoC 26m. 21*1086a531SGarmin.Chang The topckgen provides dividers and muxes which provide the clock source to other IP blocks. 22*1086a531SGarmin.Chang The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. 23*1086a531SGarmin.Chang The mcusys provides mux control to select the clock source in AP MCU. 24*1086a531SGarmin.Chang The device nodes also provide the system control capacity for configuration. 25*1086a531SGarmin.Chang 26*1086a531SGarmin.Changproperties: 27*1086a531SGarmin.Chang compatible: 28*1086a531SGarmin.Chang items: 29*1086a531SGarmin.Chang - enum: 30*1086a531SGarmin.Chang - mediatek,mt8188-apmixedsys 31*1086a531SGarmin.Chang - mediatek,mt8188-infracfg-ao 32*1086a531SGarmin.Chang - mediatek,mt8188-pericfg-ao 33*1086a531SGarmin.Chang - mediatek,mt8188-topckgen 34*1086a531SGarmin.Chang - const: syscon 35*1086a531SGarmin.Chang 36*1086a531SGarmin.Chang reg: 37*1086a531SGarmin.Chang maxItems: 1 38*1086a531SGarmin.Chang 39*1086a531SGarmin.Chang '#clock-cells': 40*1086a531SGarmin.Chang const: 1 41*1086a531SGarmin.Chang 42*1086a531SGarmin.Changrequired: 43*1086a531SGarmin.Chang - compatible 44*1086a531SGarmin.Chang - reg 45*1086a531SGarmin.Chang - '#clock-cells' 46*1086a531SGarmin.Chang 47*1086a531SGarmin.ChangadditionalProperties: false 48*1086a531SGarmin.Chang 49*1086a531SGarmin.Changexamples: 50*1086a531SGarmin.Chang - | 51*1086a531SGarmin.Chang clock-controller@10000000 { 52*1086a531SGarmin.Chang compatible = "mediatek,mt8188-topckgen", "syscon"; 53*1086a531SGarmin.Chang reg = <0x10000000 0x1000>; 54*1086a531SGarmin.Chang #clock-cells = <1>; 55*1086a531SGarmin.Chang }; 56