1*1086a531SGarmin.Chang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*1086a531SGarmin.Chang%YAML 1.2 3*1086a531SGarmin.Chang--- 4*1086a531SGarmin.Chang$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml# 5*1086a531SGarmin.Chang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1086a531SGarmin.Chang 7*1086a531SGarmin.Changtitle: MediaTek Functional Clock Controller for MT8188 8*1086a531SGarmin.Chang 9*1086a531SGarmin.Changmaintainers: 10*1086a531SGarmin.Chang - Garmin Chang <garmin.chang@mediatek.com> 11*1086a531SGarmin.Chang 12*1086a531SGarmin.Changdescription: | 13*1086a531SGarmin.Chang The clock architecture in MediaTek like below 14*1086a531SGarmin.Chang PLLs --> 15*1086a531SGarmin.Chang dividers --> 16*1086a531SGarmin.Chang muxes 17*1086a531SGarmin.Chang --> 18*1086a531SGarmin.Chang clock gate 19*1086a531SGarmin.Chang 20*1086a531SGarmin.Chang The devices provide clock gate control in different IP blocks. 21*1086a531SGarmin.Chang 22*1086a531SGarmin.Changproperties: 23*1086a531SGarmin.Chang compatible: 24*1086a531SGarmin.Chang enum: 25*1086a531SGarmin.Chang - mediatek,mt8188-adsp-audio26m 26*1086a531SGarmin.Chang - mediatek,mt8188-camsys 27*1086a531SGarmin.Chang - mediatek,mt8188-camsys-rawa 28*1086a531SGarmin.Chang - mediatek,mt8188-camsys-rawb 29*1086a531SGarmin.Chang - mediatek,mt8188-camsys-yuva 30*1086a531SGarmin.Chang - mediatek,mt8188-camsys-yuvb 31*1086a531SGarmin.Chang - mediatek,mt8188-ccusys 32*1086a531SGarmin.Chang - mediatek,mt8188-imgsys 33*1086a531SGarmin.Chang - mediatek,mt8188-imgsys-wpe1 34*1086a531SGarmin.Chang - mediatek,mt8188-imgsys-wpe2 35*1086a531SGarmin.Chang - mediatek,mt8188-imgsys-wpe3 36*1086a531SGarmin.Chang - mediatek,mt8188-imgsys1-dip-nr 37*1086a531SGarmin.Chang - mediatek,mt8188-imgsys1-dip-top 38*1086a531SGarmin.Chang - mediatek,mt8188-imp-iic-wrap-c 39*1086a531SGarmin.Chang - mediatek,mt8188-imp-iic-wrap-en 40*1086a531SGarmin.Chang - mediatek,mt8188-imp-iic-wrap-w 41*1086a531SGarmin.Chang - mediatek,mt8188-ipesys 42*1086a531SGarmin.Chang - mediatek,mt8188-mfgcfg 43*1086a531SGarmin.Chang - mediatek,mt8188-vdecsys 44*1086a531SGarmin.Chang - mediatek,mt8188-vdecsys-soc 45*1086a531SGarmin.Chang - mediatek,mt8188-vencsys 46*1086a531SGarmin.Chang - mediatek,mt8188-vppsys0 47*1086a531SGarmin.Chang - mediatek,mt8188-vppsys1 48*1086a531SGarmin.Chang - mediatek,mt8188-wpesys 49*1086a531SGarmin.Chang - mediatek,mt8188-wpesys-vpp0 50*1086a531SGarmin.Chang 51*1086a531SGarmin.Chang reg: 52*1086a531SGarmin.Chang maxItems: 1 53*1086a531SGarmin.Chang 54*1086a531SGarmin.Chang '#clock-cells': 55*1086a531SGarmin.Chang const: 1 56*1086a531SGarmin.Chang 57*1086a531SGarmin.Changrequired: 58*1086a531SGarmin.Chang - compatible 59*1086a531SGarmin.Chang - reg 60*1086a531SGarmin.Chang - '#clock-cells' 61*1086a531SGarmin.Chang 62*1086a531SGarmin.ChangadditionalProperties: false 63*1086a531SGarmin.Chang 64*1086a531SGarmin.Changexamples: 65*1086a531SGarmin.Chang - | 66*1086a531SGarmin.Chang clock-controller@11283000 { 67*1086a531SGarmin.Chang compatible = "mediatek,mt8188-imp-iic-wrap-c"; 68*1086a531SGarmin.Chang reg = <0x11283000 0x1000>; 69*1086a531SGarmin.Chang #clock-cells = <1>; 70*1086a531SGarmin.Chang }; 71*1086a531SGarmin.Chang 72