17de0b8b8SLubomir Rintel# SPDX-License-Identifier: GPL-2.0
27de0b8b8SLubomir Rintel%YAML 1.2
37de0b8b8SLubomir Rintel---
47de0b8b8SLubomir Rintel$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
57de0b8b8SLubomir Rintel$schema: http://devicetree.org/meta-schemas/core.yaml#
67de0b8b8SLubomir Rintel
7b90e0eb3SLubomir Rinteltitle: Marvell MMP2 and MMP3 Clock Controller
87de0b8b8SLubomir Rintel
97de0b8b8SLubomir Rintelmaintainers:
107de0b8b8SLubomir Rintel  - Lubomir Rintel <lkundrak@v3.sk>
117de0b8b8SLubomir Rintel
127de0b8b8SLubomir Rinteldescription: |
13b90e0eb3SLubomir Rintel  The clock subsystem on MMP2 or MMP3 generates and supplies clock to various
14b90e0eb3SLubomir Rintel  controllers within the SoC.
157de0b8b8SLubomir Rintel
167de0b8b8SLubomir Rintel  Each clock is assigned an identifier and client nodes use this identifier
177de0b8b8SLubomir Rintel  to specify the clock which they consume.
187de0b8b8SLubomir Rintel
197de0b8b8SLubomir Rintel  All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
207de0b8b8SLubomir Rintel
217de0b8b8SLubomir Rintelproperties:
227de0b8b8SLubomir Rintel  compatible:
23b90e0eb3SLubomir Rintel    enum:
24b90e0eb3SLubomir Rintel      - marvell,mmp2-clock # controller compatible with MMP2 SoC
25b90e0eb3SLubomir Rintel      - marvell,mmp3-clock # controller compatible with MMP3 SoC
267de0b8b8SLubomir Rintel
277de0b8b8SLubomir Rintel  reg:
287de0b8b8SLubomir Rintel    items:
297de0b8b8SLubomir Rintel      - description: MPMU register region
307de0b8b8SLubomir Rintel      - description: APMU register region
317de0b8b8SLubomir Rintel      - description: APBC register region
327de0b8b8SLubomir Rintel
337de0b8b8SLubomir Rintel  reg-names:
347de0b8b8SLubomir Rintel    items:
357de0b8b8SLubomir Rintel      - const: mpmu
367de0b8b8SLubomir Rintel      - const: apmu
377de0b8b8SLubomir Rintel      - const: apbc
387de0b8b8SLubomir Rintel
397de0b8b8SLubomir Rintel  '#clock-cells':
407de0b8b8SLubomir Rintel    const: 1
417de0b8b8SLubomir Rintel
427de0b8b8SLubomir Rintel  '#reset-cells':
437de0b8b8SLubomir Rintel    const: 1
447de0b8b8SLubomir Rintel
45ec6bbddeSLubomir Rintel  '#power-domain-cells':
46ec6bbddeSLubomir Rintel    const: 1
47ec6bbddeSLubomir Rintel
487de0b8b8SLubomir Rintelrequired:
497de0b8b8SLubomir Rintel  - compatible
507de0b8b8SLubomir Rintel  - reg
517de0b8b8SLubomir Rintel  - reg-names
527de0b8b8SLubomir Rintel  - '#clock-cells'
537de0b8b8SLubomir Rintel  - '#reset-cells'
54ec6bbddeSLubomir Rintel  - '#power-domain-cells'
557de0b8b8SLubomir Rintel
567de0b8b8SLubomir RinteladditionalProperties: false
577de0b8b8SLubomir Rintel
587de0b8b8SLubomir Rintelexamples:
597de0b8b8SLubomir Rintel  - |
607de0b8b8SLubomir Rintel    clock-controller@d4050000 {
617de0b8b8SLubomir Rintel      compatible = "marvell,mmp2-clock";
627de0b8b8SLubomir Rintel      reg = <0xd4050000 0x1000>,
637de0b8b8SLubomir Rintel            <0xd4282800 0x400>,
647de0b8b8SLubomir Rintel            <0xd4015000 0x1000>;
657de0b8b8SLubomir Rintel      reg-names = "mpmu", "apmu", "apbc";
667de0b8b8SLubomir Rintel      #clock-cells = <1>;
677de0b8b8SLubomir Rintel      #reset-cells = <1>;
68ec6bbddeSLubomir Rintel      #power-domain-cells = <1>;
697de0b8b8SLubomir Rintel    };
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