1c1f86f2fSAntoine TenartDevice Tree Clock bindings for Marvell Berlin 2c1f86f2fSAntoine Tenart 3c1f86f2fSAntoine TenartThis binding uses the common clock binding[1]. 4c1f86f2fSAntoine Tenart 5c1f86f2fSAntoine Tenart[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6c1f86f2fSAntoine Tenart 7c1f86f2fSAntoine TenartClock related registers are spread among the chip control registers. Berlin 8c1f86f2fSAntoine Tenartclock node should be a sub-node of the chip controller node. Marvell Berlin2 9c1f86f2fSAntoine Tenart(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some 10c1f86f2fSAntoine Tenartminor differences in features and register layout. 11c1f86f2fSAntoine Tenart 12c1f86f2fSAntoine TenartRequired properties: 13c1f86f2fSAntoine Tenart- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk" 14c1f86f2fSAntoine Tenart- #clock-cells: must be 1 15c1f86f2fSAntoine Tenart- clocks: must be the input parent clock phandle 16c1f86f2fSAntoine Tenart- clock-names: name of the input parent clock 17c1f86f2fSAntoine Tenart Allowed clock-names for the reference clocks are 18c1f86f2fSAntoine Tenart "refclk" for the SoCs oscillator input on all SoCs, 19c1f86f2fSAntoine Tenart and SoC-specific input clocks for 20c1f86f2fSAntoine Tenart BG2/BG2CD: "video_ext0" for the external video clock input 21c1f86f2fSAntoine Tenart 22c1f86f2fSAntoine Tenart 23c1f86f2fSAntoine TenartExample: 24c1f86f2fSAntoine Tenart 25c1f86f2fSAntoine Tenartchip_clk: clock { 26c1f86f2fSAntoine Tenart compatible = "marvell,berlin2q-clk"; 27c1f86f2fSAntoine Tenart 28c1f86f2fSAntoine Tenart #clock-cells = <1>; 29c1f86f2fSAntoine Tenart clocks = <&refclk>; 30c1f86f2fSAntoine Tenart clock-names = "refclk"; 31c1f86f2fSAntoine Tenart}; 32