1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
8
9description: |
10  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
11  clock generators providing from 3 to 12 output clocks.
12
13  When referencing the provided clock in the DT using phandle and clock
14  specifier, the following mapping applies:
15
16  - 5P49V5923:
17    0 -- OUT0_SEL_I2CB
18    1 -- OUT1
19    2 -- OUT2
20
21  - 5P49V5933:
22    0 -- OUT0_SEL_I2CB
23    1 -- OUT1
24    2 -- OUT4
25
26  - other parts:
27    0 -- OUT0_SEL_I2CB
28    1 -- OUT1
29    2 -- OUT2
30    3 -- OUT3
31    4 -- OUT4
32
33maintainers:
34  - Luca Ceresoli <luca@lucaceresoli.net>
35
36properties:
37  compatible:
38    enum:
39      - idt,5p49v5923
40      - idt,5p49v5925
41      - idt,5p49v5933
42      - idt,5p49v5935
43      - idt,5p49v6901
44      - idt,5p49v6965
45
46  reg:
47    description: I2C device address
48    enum: [ 0x68, 0x6a ]
49
50  '#clock-cells':
51    const: 1
52
53  clock-names:
54    minItems: 1
55    maxItems: 2
56    items:
57      enum: [ xin, clkin ]
58  clocks:
59    minItems: 1
60    maxItems: 2
61
62patternProperties:
63  "^OUT[1-4]$":
64    type: object
65    description:
66      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
67      Configuration" in the Versaclock 5/6/6E Family Register Description
68      and Programming Guide.
69    properties:
70      idt,mode:
71        description:
72          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
73        $ref: /schemas/types.yaml#/definitions/uint32
74        minimum: 0
75        maximum: 6
76      idt,voltage-microvolt:
77        description: The output drive voltage.
78        enum: [ 1800000, 2500000, 3300000 ]
79      idt,slew-percent:
80        description: The Slew rate control for CMOS single-ended.
81        $ref: /schemas/types.yaml#/definitions/uint32
82        enum: [ 80, 85, 90, 100 ]
83
84required:
85  - compatible
86  - reg
87  - '#clock-cells'
88
89allOf:
90  - if:
91      properties:
92        compatible:
93          enum:
94            - idt,5p49v5933
95            - idt,5p49v5935
96    then:
97      # Devices with builtin crystal + optional external input
98      properties:
99        clock-names:
100          const: clkin
101        clocks:
102          maxItems: 1
103    else:
104      # Devices without builtin crystal
105      required:
106        - clock-names
107        - clocks
108
109additionalProperties: false
110
111examples:
112  - |
113    #include <dt-bindings/clk/versaclock.h>
114
115    /* 25MHz reference crystal */
116    ref25: ref25m {
117        compatible = "fixed-clock";
118        #clock-cells = <0>;
119        clock-frequency = <25000000>;
120    };
121
122    i2c@0 {
123        reg = <0x0 0x100>;
124        #address-cells = <1>;
125        #size-cells = <0>;
126
127        /* IDT 5P49V5923 I2C clock generator */
128        vc5: clock-generator@6a {
129            compatible = "idt,5p49v5923";
130            reg = <0x6a>;
131            #clock-cells = <1>;
132
133            /* Connect XIN input to 25MHz reference */
134            clocks = <&ref25m>;
135            clock-names = "xin";
136
137            OUT1 {
138                idt,drive-mode = <VC5_CMOSD>;
139                idt,voltage-microvolts = <1800000>;
140                idt,slew-percent = <80>;
141            };
142
143            OUT4 {
144                idt,drive-mode = <VC5_LVDS>;
145            };
146        };
147    };
148
149    /* Consumer referencing the 5P49V5923 pin OUT1 */
150    consumer {
151        /* ... */
152        clocks = <&vc5 1>;
153        /* ... */
154    };
155
156...
157