1*a70cd8cdSShengjiu Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a70cd8cdSShengjiu Wang%YAML 1.2 3*a70cd8cdSShengjiu Wang--- 4*a70cd8cdSShengjiu Wang$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml# 5*a70cd8cdSShengjiu Wang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a70cd8cdSShengjiu Wang 7*a70cd8cdSShengjiu Wangtitle: NXP i.MX8 Audio Clock Mux 8*a70cd8cdSShengjiu Wang 9*a70cd8cdSShengjiu Wangmaintainers: 10*a70cd8cdSShengjiu Wang - Shengjiu Wang <shengjiu.wang@nxp.com> 11*a70cd8cdSShengjiu Wang 12*a70cd8cdSShengjiu Wangdescription: | 13*a70cd8cdSShengjiu Wang NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP 14*a70cd8cdSShengjiu Wang used to control Audio related clock on the SoC. 15*a70cd8cdSShengjiu Wang 16*a70cd8cdSShengjiu Wangproperties: 17*a70cd8cdSShengjiu Wang compatible: 18*a70cd8cdSShengjiu Wang enum: 19*a70cd8cdSShengjiu Wang - fsl,imx8dxl-acm 20*a70cd8cdSShengjiu Wang - fsl,imx8qm-acm 21*a70cd8cdSShengjiu Wang - fsl,imx8qxp-acm 22*a70cd8cdSShengjiu Wang 23*a70cd8cdSShengjiu Wang reg: 24*a70cd8cdSShengjiu Wang maxItems: 1 25*a70cd8cdSShengjiu Wang 26*a70cd8cdSShengjiu Wang power-domains: 27*a70cd8cdSShengjiu Wang minItems: 13 28*a70cd8cdSShengjiu Wang maxItems: 21 29*a70cd8cdSShengjiu Wang 30*a70cd8cdSShengjiu Wang '#clock-cells': 31*a70cd8cdSShengjiu Wang const: 1 32*a70cd8cdSShengjiu Wang description: 33*a70cd8cdSShengjiu Wang The clock consumer should specify the desired clock by having the clock 34*a70cd8cdSShengjiu Wang ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h 35*a70cd8cdSShengjiu Wang for the full list of i.MX8 ACM clock IDs. 36*a70cd8cdSShengjiu Wang 37*a70cd8cdSShengjiu Wang clocks: 38*a70cd8cdSShengjiu Wang minItems: 13 39*a70cd8cdSShengjiu Wang maxItems: 27 40*a70cd8cdSShengjiu Wang 41*a70cd8cdSShengjiu Wang clock-names: 42*a70cd8cdSShengjiu Wang minItems: 13 43*a70cd8cdSShengjiu Wang maxItems: 27 44*a70cd8cdSShengjiu Wang 45*a70cd8cdSShengjiu Wangrequired: 46*a70cd8cdSShengjiu Wang - compatible 47*a70cd8cdSShengjiu Wang - reg 48*a70cd8cdSShengjiu Wang - power-domains 49*a70cd8cdSShengjiu Wang - '#clock-cells' 50*a70cd8cdSShengjiu Wang - clocks 51*a70cd8cdSShengjiu Wang - clock-names 52*a70cd8cdSShengjiu Wang 53*a70cd8cdSShengjiu WangallOf: 54*a70cd8cdSShengjiu Wang - if: 55*a70cd8cdSShengjiu Wang properties: 56*a70cd8cdSShengjiu Wang compatible: 57*a70cd8cdSShengjiu Wang contains: 58*a70cd8cdSShengjiu Wang enum: 59*a70cd8cdSShengjiu Wang - fsl,imx8qxp-acm 60*a70cd8cdSShengjiu Wang then: 61*a70cd8cdSShengjiu Wang properties: 62*a70cd8cdSShengjiu Wang power-domains: 63*a70cd8cdSShengjiu Wang items: 64*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_CLK_0 65*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_CLK_1 66*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MCLK_OUT_0 67*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MCLK_OUT_1 68*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_PLL_0 69*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_PLL_1 70*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_ASRC_0 71*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_ASRC_1 72*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_ESAI_0 73*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_0 74*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_1 75*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_2 76*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_3 77*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_4 78*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_5 79*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SPDIF_0 80*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MQS_0 81*a70cd8cdSShengjiu Wang 82*a70cd8cdSShengjiu Wang clocks: 83*a70cd8cdSShengjiu Wang minItems: 18 84*a70cd8cdSShengjiu Wang maxItems: 18 85*a70cd8cdSShengjiu Wang 86*a70cd8cdSShengjiu Wang clock-names: 87*a70cd8cdSShengjiu Wang items: 88*a70cd8cdSShengjiu Wang - const: aud_rec_clk0_lpcg_clk 89*a70cd8cdSShengjiu Wang - const: aud_rec_clk1_lpcg_clk 90*a70cd8cdSShengjiu Wang - const: aud_pll_div_clk0_lpcg_clk 91*a70cd8cdSShengjiu Wang - const: aud_pll_div_clk1_lpcg_clk 92*a70cd8cdSShengjiu Wang - const: ext_aud_mclk0 93*a70cd8cdSShengjiu Wang - const: ext_aud_mclk1 94*a70cd8cdSShengjiu Wang - const: esai0_rx_clk 95*a70cd8cdSShengjiu Wang - const: esai0_rx_hf_clk 96*a70cd8cdSShengjiu Wang - const: esai0_tx_clk 97*a70cd8cdSShengjiu Wang - const: esai0_tx_hf_clk 98*a70cd8cdSShengjiu Wang - const: spdif0_rx 99*a70cd8cdSShengjiu Wang - const: sai0_rx_bclk 100*a70cd8cdSShengjiu Wang - const: sai0_tx_bclk 101*a70cd8cdSShengjiu Wang - const: sai1_rx_bclk 102*a70cd8cdSShengjiu Wang - const: sai1_tx_bclk 103*a70cd8cdSShengjiu Wang - const: sai2_rx_bclk 104*a70cd8cdSShengjiu Wang - const: sai3_rx_bclk 105*a70cd8cdSShengjiu Wang - const: sai4_rx_bclk 106*a70cd8cdSShengjiu Wang 107*a70cd8cdSShengjiu Wang - if: 108*a70cd8cdSShengjiu Wang properties: 109*a70cd8cdSShengjiu Wang compatible: 110*a70cd8cdSShengjiu Wang contains: 111*a70cd8cdSShengjiu Wang enum: 112*a70cd8cdSShengjiu Wang - fsl,imx8qm-acm 113*a70cd8cdSShengjiu Wang then: 114*a70cd8cdSShengjiu Wang properties: 115*a70cd8cdSShengjiu Wang power-domains: 116*a70cd8cdSShengjiu Wang items: 117*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_CLK_0 118*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_CLK_1 119*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MCLK_OUT_0 120*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MCLK_OUT_1 121*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_PLL_0 122*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_PLL_1 123*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_ASRC_0 124*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_ASRC_1 125*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_ESAI_0 126*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_ESAI_1 127*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_0 128*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_1 129*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_2 130*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_3 131*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_4 132*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_5 133*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_6 134*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_7 135*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SPDIF_0 136*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SPDIF_1 137*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MQS_0 138*a70cd8cdSShengjiu Wang 139*a70cd8cdSShengjiu Wang clocks: 140*a70cd8cdSShengjiu Wang minItems: 27 141*a70cd8cdSShengjiu Wang maxItems: 27 142*a70cd8cdSShengjiu Wang 143*a70cd8cdSShengjiu Wang clock-names: 144*a70cd8cdSShengjiu Wang items: 145*a70cd8cdSShengjiu Wang - const: aud_rec_clk0_lpcg_clk 146*a70cd8cdSShengjiu Wang - const: aud_rec_clk1_lpcg_clk 147*a70cd8cdSShengjiu Wang - const: aud_pll_div_clk0_lpcg_clk 148*a70cd8cdSShengjiu Wang - const: aud_pll_div_clk1_lpcg_clk 149*a70cd8cdSShengjiu Wang - const: mlb_clk 150*a70cd8cdSShengjiu Wang - const: hdmi_rx_mclk 151*a70cd8cdSShengjiu Wang - const: ext_aud_mclk0 152*a70cd8cdSShengjiu Wang - const: ext_aud_mclk1 153*a70cd8cdSShengjiu Wang - const: esai0_rx_clk 154*a70cd8cdSShengjiu Wang - const: esai0_rx_hf_clk 155*a70cd8cdSShengjiu Wang - const: esai0_tx_clk 156*a70cd8cdSShengjiu Wang - const: esai0_tx_hf_clk 157*a70cd8cdSShengjiu Wang - const: esai1_rx_clk 158*a70cd8cdSShengjiu Wang - const: esai1_rx_hf_clk 159*a70cd8cdSShengjiu Wang - const: esai1_tx_clk 160*a70cd8cdSShengjiu Wang - const: esai1_tx_hf_clk 161*a70cd8cdSShengjiu Wang - const: spdif0_rx 162*a70cd8cdSShengjiu Wang - const: spdif1_rx 163*a70cd8cdSShengjiu Wang - const: sai0_rx_bclk 164*a70cd8cdSShengjiu Wang - const: sai0_tx_bclk 165*a70cd8cdSShengjiu Wang - const: sai1_rx_bclk 166*a70cd8cdSShengjiu Wang - const: sai1_tx_bclk 167*a70cd8cdSShengjiu Wang - const: sai2_rx_bclk 168*a70cd8cdSShengjiu Wang - const: sai3_rx_bclk 169*a70cd8cdSShengjiu Wang - const: sai4_rx_bclk 170*a70cd8cdSShengjiu Wang - const: sai5_tx_bclk 171*a70cd8cdSShengjiu Wang - const: sai6_rx_bclk 172*a70cd8cdSShengjiu Wang 173*a70cd8cdSShengjiu Wang - if: 174*a70cd8cdSShengjiu Wang properties: 175*a70cd8cdSShengjiu Wang compatible: 176*a70cd8cdSShengjiu Wang contains: 177*a70cd8cdSShengjiu Wang enum: 178*a70cd8cdSShengjiu Wang - fsl,imx8dxl-acm 179*a70cd8cdSShengjiu Wang then: 180*a70cd8cdSShengjiu Wang properties: 181*a70cd8cdSShengjiu Wang power-domains: 182*a70cd8cdSShengjiu Wang items: 183*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_CLK_0 184*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_CLK_1 185*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MCLK_OUT_0 186*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MCLK_OUT_1 187*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_PLL_0 188*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_AUDIO_PLL_1 189*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_ASRC_0 190*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_0 191*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_1 192*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_2 193*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SAI_3 194*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_SPDIF_0 195*a70cd8cdSShengjiu Wang - description: power domain of IMX_SC_R_MQS_0 196*a70cd8cdSShengjiu Wang 197*a70cd8cdSShengjiu Wang clocks: 198*a70cd8cdSShengjiu Wang minItems: 13 199*a70cd8cdSShengjiu Wang maxItems: 13 200*a70cd8cdSShengjiu Wang 201*a70cd8cdSShengjiu Wang clock-names: 202*a70cd8cdSShengjiu Wang items: 203*a70cd8cdSShengjiu Wang - const: aud_rec_clk0_lpcg_clk 204*a70cd8cdSShengjiu Wang - const: aud_rec_clk1_lpcg_clk 205*a70cd8cdSShengjiu Wang - const: aud_pll_div_clk0_lpcg_clk 206*a70cd8cdSShengjiu Wang - const: aud_pll_div_clk1_lpcg_clk 207*a70cd8cdSShengjiu Wang - const: ext_aud_mclk0 208*a70cd8cdSShengjiu Wang - const: ext_aud_mclk1 209*a70cd8cdSShengjiu Wang - const: spdif0_rx 210*a70cd8cdSShengjiu Wang - const: sai0_rx_bclk 211*a70cd8cdSShengjiu Wang - const: sai0_tx_bclk 212*a70cd8cdSShengjiu Wang - const: sai1_rx_bclk 213*a70cd8cdSShengjiu Wang - const: sai1_tx_bclk 214*a70cd8cdSShengjiu Wang - const: sai2_rx_bclk 215*a70cd8cdSShengjiu Wang - const: sai3_rx_bclk 216*a70cd8cdSShengjiu Wang 217*a70cd8cdSShengjiu WangadditionalProperties: false 218*a70cd8cdSShengjiu Wang 219*a70cd8cdSShengjiu Wangexamples: 220*a70cd8cdSShengjiu Wang # Clock Control Module node: 221*a70cd8cdSShengjiu Wang - | 222*a70cd8cdSShengjiu Wang #include <dt-bindings/clock/imx8-lpcg.h> 223*a70cd8cdSShengjiu Wang #include <dt-bindings/firmware/imx/rsrc.h> 224*a70cd8cdSShengjiu Wang 225*a70cd8cdSShengjiu Wang clock-controller@59e00000 { 226*a70cd8cdSShengjiu Wang compatible = "fsl,imx8qxp-acm"; 227*a70cd8cdSShengjiu Wang reg = <0x59e00000 0x1d0000>; 228*a70cd8cdSShengjiu Wang #clock-cells = <1>; 229*a70cd8cdSShengjiu Wang power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, 230*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_AUDIO_CLK_1>, 231*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_MCLK_OUT_0>, 232*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_MCLK_OUT_1>, 233*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_AUDIO_PLL_0>, 234*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_AUDIO_PLL_1>, 235*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_ASRC_0>, 236*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_ASRC_1>, 237*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_ESAI_0>, 238*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_SAI_0>, 239*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_SAI_1>, 240*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_SAI_2>, 241*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_SAI_3>, 242*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_SAI_4>, 243*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_SAI_5>, 244*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_SPDIF_0>, 245*a70cd8cdSShengjiu Wang <&pd IMX_SC_R_MQS_0>; 246*a70cd8cdSShengjiu Wang clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, 247*a70cd8cdSShengjiu Wang <&aud_rec1_lpcg IMX_LPCG_CLK_0>, 248*a70cd8cdSShengjiu Wang <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 249*a70cd8cdSShengjiu Wang <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 250*a70cd8cdSShengjiu Wang <&clk_ext_aud_mclk0>, 251*a70cd8cdSShengjiu Wang <&clk_ext_aud_mclk1>, 252*a70cd8cdSShengjiu Wang <&clk_esai0_rx_clk>, 253*a70cd8cdSShengjiu Wang <&clk_esai0_rx_hf_clk>, 254*a70cd8cdSShengjiu Wang <&clk_esai0_tx_clk>, 255*a70cd8cdSShengjiu Wang <&clk_esai0_tx_hf_clk>, 256*a70cd8cdSShengjiu Wang <&clk_spdif0_rx>, 257*a70cd8cdSShengjiu Wang <&clk_sai0_rx_bclk>, 258*a70cd8cdSShengjiu Wang <&clk_sai0_tx_bclk>, 259*a70cd8cdSShengjiu Wang <&clk_sai1_rx_bclk>, 260*a70cd8cdSShengjiu Wang <&clk_sai1_tx_bclk>, 261*a70cd8cdSShengjiu Wang <&clk_sai2_rx_bclk>, 262*a70cd8cdSShengjiu Wang <&clk_sai3_rx_bclk>, 263*a70cd8cdSShengjiu Wang <&clk_sai4_rx_bclk>; 264*a70cd8cdSShengjiu Wang clock-names = "aud_rec_clk0_lpcg_clk", 265*a70cd8cdSShengjiu Wang "aud_rec_clk1_lpcg_clk", 266*a70cd8cdSShengjiu Wang "aud_pll_div_clk0_lpcg_clk", 267*a70cd8cdSShengjiu Wang "aud_pll_div_clk1_lpcg_clk", 268*a70cd8cdSShengjiu Wang "ext_aud_mclk0", 269*a70cd8cdSShengjiu Wang "ext_aud_mclk1", 270*a70cd8cdSShengjiu Wang "esai0_rx_clk", 271*a70cd8cdSShengjiu Wang "esai0_rx_hf_clk", 272*a70cd8cdSShengjiu Wang "esai0_tx_clk", 273*a70cd8cdSShengjiu Wang "esai0_tx_hf_clk", 274*a70cd8cdSShengjiu Wang "spdif0_rx", 275*a70cd8cdSShengjiu Wang "sai0_rx_bclk", 276*a70cd8cdSShengjiu Wang "sai0_tx_bclk", 277*a70cd8cdSShengjiu Wang "sai1_rx_bclk", 278*a70cd8cdSShengjiu Wang "sai1_tx_bclk", 279*a70cd8cdSShengjiu Wang "sai2_rx_bclk", 280*a70cd8cdSShengjiu Wang "sai3_rx_bclk", 281*a70cd8cdSShengjiu Wang "sai4_rx_bclk"; 282*a70cd8cdSShengjiu Wang }; 283