17d9e0b12SMarek Behún# SPDX-License-Identifier: GPL-2.0 27d9e0b12SMarek Behún%YAML 1.2 37d9e0b12SMarek Behún--- 47d9e0b12SMarek Behún$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml# 57d9e0b12SMarek Behún$schema: http://devicetree.org/meta-schemas/core.yaml# 67d9e0b12SMarek Behún 7*9d69d47fSKrzysztof Kozlowskititle: Simple memory mapped IO fixed-rate clock sources 87d9e0b12SMarek Behún 97d9e0b12SMarek Behúndescription: 107d9e0b12SMarek Behún This binding describes a fixed-rate clock for which the frequency can 117d9e0b12SMarek Behún be read from a single 32-bit memory mapped I/O register. 127d9e0b12SMarek Behún 137d9e0b12SMarek Behún It was designed for test systems, like FPGA, not for complete, 147d9e0b12SMarek Behún finished SoCs. 157d9e0b12SMarek Behún 167d9e0b12SMarek Behúnmaintainers: 177d9e0b12SMarek Behún - Jan Kotas <jank@cadence.com> 187d9e0b12SMarek Behún 197d9e0b12SMarek Behúnproperties: 207d9e0b12SMarek Behún compatible: 217d9e0b12SMarek Behún const: fixed-mmio-clock 227d9e0b12SMarek Behún 237d9e0b12SMarek Behún reg: 247d9e0b12SMarek Behún maxItems: 1 257d9e0b12SMarek Behún 267d9e0b12SMarek Behún "#clock-cells": 277d9e0b12SMarek Behún const: 0 287d9e0b12SMarek Behún 297d9e0b12SMarek Behún clock-output-names: 307d9e0b12SMarek Behún maxItems: 1 317d9e0b12SMarek Behún 327d9e0b12SMarek Behúnrequired: 337d9e0b12SMarek Behún - compatible 347d9e0b12SMarek Behún - reg 357d9e0b12SMarek Behún - "#clock-cells" 367d9e0b12SMarek Behún 377d9e0b12SMarek BehúnadditionalProperties: false 387d9e0b12SMarek Behún 397d9e0b12SMarek Behúnexamples: 407d9e0b12SMarek Behún - | 417d9e0b12SMarek Behún sysclock: sysclock@fd020004 { 427d9e0b12SMarek Behún compatible = "fixed-mmio-clock"; 437d9e0b12SMarek Behún #clock-cells = <0>; 447d9e0b12SMarek Behún reg = <0xfd020004 0x4>; 457d9e0b12SMarek Behún clock-output-names = "sysclk"; 467d9e0b12SMarek Behún }; 477d9e0b12SMarek Behún... 48