178c7d8f9SLinus Walleij# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 278c7d8f9SLinus Walleij%YAML 1.2 378c7d8f9SLinus Walleij--- 478c7d8f9SLinus Walleij$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# 578c7d8f9SLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml# 678c7d8f9SLinus Walleij 778c7d8f9SLinus Walleijtitle: ARM System Controller ICST Clocks 878c7d8f9SLinus Walleij 978c7d8f9SLinus Walleijmaintainers: 1078c7d8f9SLinus Walleij - Linus Walleij <linusw@kernel.org> 1178c7d8f9SLinus Walleij 1278c7d8f9SLinus Walleijdescription: | 1378c7d8f9SLinus Walleij The ICS525 and ICS307 oscillators are produced by Integrated 1478c7d8f9SLinus Walleij Devices Technology (IDT). ARM integrated these oscillators deeply into their 1578c7d8f9SLinus Walleij reference designs by adding special control registers that manage such 1678c7d8f9SLinus Walleij oscillators to their system controllers. 1778c7d8f9SLinus Walleij 1878c7d8f9SLinus Walleij The various ARM system controllers contain logic to serialize and initialize 1978c7d8f9SLinus Walleij an ICST clock request after a write to the 32 bit register at an offset 2078c7d8f9SLinus Walleij into the system controller. Furthermore, to even be able to alter one of 2178c7d8f9SLinus Walleij these frequencies, the system controller must first be unlocked by 2278c7d8f9SLinus Walleij writing a special token to another offset in the system controller. 2378c7d8f9SLinus Walleij 2478c7d8f9SLinus Walleij Some ARM hardware contain special versions of the serial interface that only 2578c7d8f9SLinus Walleij connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to 2678c7d8f9SLinus Walleij different values and sometimes also hard-wires the output divider. They 2778c7d8f9SLinus Walleij therefore have special compatible strings as per this table (the OD value is 2878c7d8f9SLinus Walleij the value on the pins, not the resulting output divider). 2978c7d8f9SLinus Walleij 3078c7d8f9SLinus Walleij In the core modules and logic tiles, the ICST is a configurable clock fed 3178c7d8f9SLinus Walleij from a 24 MHz clock on the motherboard (usually the main crystal) used for 3278c7d8f9SLinus Walleij generating e.g. video clocks. It is located on the core module and there is 3378c7d8f9SLinus Walleij only one of these. This clock node must be a subnode of the core module. 3478c7d8f9SLinus Walleij 3578c7d8f9SLinus Walleij Hardware variant RDW OD VDW 3678c7d8f9SLinus Walleij 3778c7d8f9SLinus Walleij Integrator/AP 22 1 Bit 8 0, rest variable 3878c7d8f9SLinus Walleij integratorap-cm 3978c7d8f9SLinus Walleij 4078c7d8f9SLinus Walleij Integrator/AP 46 3 Bit 8 0, rest variable 4178c7d8f9SLinus Walleij integratorap-sys 4278c7d8f9SLinus Walleij 4378c7d8f9SLinus Walleij Integrator/AP 22 or 1 17 or (33 or 25 MHz) 4478c7d8f9SLinus Walleij integratorap-pci 14 1 14 4578c7d8f9SLinus Walleij 4678c7d8f9SLinus Walleij Integrator/CP 22 variable Bit 8 0, rest variable 4778c7d8f9SLinus Walleij integratorcp-cm-core 4878c7d8f9SLinus Walleij 4978c7d8f9SLinus Walleij Integrator/CP 22 variable Bit 8 0, rest variable 5078c7d8f9SLinus Walleij integratorcp-cm-mem 5178c7d8f9SLinus Walleij 5278c7d8f9SLinus Walleij The ICST oscillator must be provided inside a system controller node. 5378c7d8f9SLinus Walleij 5478c7d8f9SLinus Walleijproperties: 5578c7d8f9SLinus Walleij "#clock-cells": 5678c7d8f9SLinus Walleij const: 0 5778c7d8f9SLinus Walleij 5878c7d8f9SLinus Walleij compatible: 5978c7d8f9SLinus Walleij enum: 6078c7d8f9SLinus Walleij - arm,syscon-icst525 6178c7d8f9SLinus Walleij - arm,syscon-icst307 6278c7d8f9SLinus Walleij - arm,syscon-icst525-integratorap-cm 6378c7d8f9SLinus Walleij - arm,syscon-icst525-integratorap-sys 6478c7d8f9SLinus Walleij - arm,syscon-icst525-integratorap-pci 6578c7d8f9SLinus Walleij - arm,syscon-icst525-integratorcp-cm-core 6678c7d8f9SLinus Walleij - arm,syscon-icst525-integratorcp-cm-mem 6778c7d8f9SLinus Walleij - arm,integrator-cm-auxosc 6878c7d8f9SLinus Walleij - arm,versatile-cm-auxosc 69*91f93c38SRob Herring - arm,impd1-vco1 70*91f93c38SRob Herring - arm,impd1-vco2 7178c7d8f9SLinus Walleij 7278c7d8f9SLinus Walleij clocks: 7378c7d8f9SLinus Walleij description: Parent clock for the ICST VCO 7478c7d8f9SLinus Walleij maxItems: 1 7578c7d8f9SLinus Walleij 7678c7d8f9SLinus Walleij clock-output-names: 7778c7d8f9SLinus Walleij maxItems: 1 7878c7d8f9SLinus Walleij 7978c7d8f9SLinus Walleij lock-offset: 8078c7d8f9SLinus Walleij $ref: '/schemas/types.yaml#/definitions/uint32' 8178c7d8f9SLinus Walleij description: Offset to the unlocking register for the oscillator 8278c7d8f9SLinus Walleij 8378c7d8f9SLinus Walleij vco-offset: 8478c7d8f9SLinus Walleij $ref: '/schemas/types.yaml#/definitions/uint32' 8578c7d8f9SLinus Walleij description: Offset to the VCO register for the oscillator 8678c7d8f9SLinus Walleij 8778c7d8f9SLinus Walleijrequired: 8878c7d8f9SLinus Walleij - "#clock-cells" 8978c7d8f9SLinus Walleij - compatible 9078c7d8f9SLinus Walleij - clocks 9178c7d8f9SLinus Walleij 925be478f9SRob HerringadditionalProperties: false 935be478f9SRob Herring 9478c7d8f9SLinus Walleijexamples: 9578c7d8f9SLinus Walleij - | 96ec76f57dSFabio Estevam vco1: clock { 9778c7d8f9SLinus Walleij compatible = "arm,impd1-vco1"; 9878c7d8f9SLinus Walleij #clock-cells = <0>; 9978c7d8f9SLinus Walleij lock-offset = <0x08>; 10078c7d8f9SLinus Walleij vco-offset = <0x00>; 10178c7d8f9SLinus Walleij clocks = <&sysclk>; 10278c7d8f9SLinus Walleij clock-output-names = "IM-PD1-VCO1"; 10378c7d8f9SLinus Walleij }; 10478c7d8f9SLinus Walleij 10578c7d8f9SLinus Walleij... 106