112545fa3SCarlo Caione* Amlogic Meson8b Clock and Reset Unit
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312545fa3SCarlo CaioneThe Amlogic Meson8b clock controller generates and supplies clock to various
412545fa3SCarlo Caionecontrollers within the SoC.
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612545fa3SCarlo CaioneRequired Properties:
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812545fa3SCarlo Caione- compatible: should be "amlogic,meson8b-clkc"
912545fa3SCarlo Caione- reg: it must be composed by two tuples:
1012545fa3SCarlo Caione	0) physical base address of the xtal register and length of memory
1112545fa3SCarlo Caione	   mapped region.
1212545fa3SCarlo Caione	1) physical base address of the clock controller and length of memory
1312545fa3SCarlo Caione	   mapped region.
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1512545fa3SCarlo Caione- #clock-cells: should be 1.
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1712545fa3SCarlo CaioneEach clock is assigned an identifier and client nodes can use this identifier
1812545fa3SCarlo Caioneto specify the clock which they consume. All available clocks are defined as
1912545fa3SCarlo Caionepreprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
2012545fa3SCarlo Caioneused in device tree sources.
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2212545fa3SCarlo CaioneExample: Clock controller node:
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2412545fa3SCarlo Caione	clkc: clock-controller@c1104000 {
2512545fa3SCarlo Caione		#clock-cells = <1>;
2612545fa3SCarlo Caione		compatible = "amlogic,meson8b-clkc";
2712545fa3SCarlo Caione		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
2812545fa3SCarlo Caione	};
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3112545fa3SCarlo CaioneExample: UART controller node that consumes the clock generated by the clock
3212545fa3SCarlo Caione  controller:
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3412545fa3SCarlo Caione	uart_AO: serial@c81004c0 {
3512545fa3SCarlo Caione		compatible = "amlogic,meson-uart";
3612545fa3SCarlo Caione		reg = <0xc81004c0 0x14>;
3712545fa3SCarlo Caione		interrupts = <0 90 1>;
3812545fa3SCarlo Caione		clocks = <&clkc CLKID_CLK81>;
3912545fa3SCarlo Caione		status = "disabled";
4012545fa3SCarlo Caione	};
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