1042000b0SDinh NguyenDevice Tree Clock bindings for Altera's SoCFPGA platform 2042000b0SDinh Nguyen 3042000b0SDinh NguyenThis binding uses the common clock binding[1]. 4042000b0SDinh Nguyen 5042000b0SDinh Nguyen[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6042000b0SDinh Nguyen 7042000b0SDinh NguyenRequired properties: 8042000b0SDinh Nguyen- compatible : shall be one of the following: 9042000b0SDinh Nguyen "altr,socfpga-pll-clock" - for a PLL clock 10042000b0SDinh Nguyen "altr,socfpga-perip-clock" - The peripheral clock divided from the 11042000b0SDinh Nguyen PLL clock. 12a92b83afSDinh Nguyen "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and 13a92b83afSDinh Nguyen can get gated. 14a92b83afSDinh Nguyen 15042000b0SDinh Nguyen- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. 16042000b0SDinh Nguyen- clocks : shall be the input parent clock phandle for the clock. This is 17042000b0SDinh Nguyen either an oscillator or a pll output. 18042000b0SDinh Nguyen- #clock-cells : from common clock binding, shall be set to 0. 19042000b0SDinh Nguyen 20042000b0SDinh NguyenOptional properties: 21042000b0SDinh Nguyen- fixed-divider : If clocks have a fixed divider value, use this property. 22a92b83afSDinh Nguyen- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register 23a92b83afSDinh Nguyen and the bit index. 248cb289edSDinh Nguyen- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains 258cb289edSDinh Nguyen the divider register, bit shift, and width. 26044abbdeSDinh Nguyen- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls 27044abbdeSDinh Nguyen the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second 28044abbdeSDinh Nguyen value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct 29044abbdeSDinh Nguyen hold/delay times that is needed for the SD/MMC CIU clock. The values of both 30044abbdeSDinh Nguyen can be 0-315 degrees, in 45 degree increments. 31