1*dc8ea920SConor Dooley# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2*dc8ea920SConor Dooley%YAML 1.2 3*dc8ea920SConor Dooley--- 4*dc8ea920SConor Dooley$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml# 5*dc8ea920SConor Dooley$schema: http://devicetree.org/meta-schemas/core.yaml# 6*dc8ea920SConor Dooley 7*dc8ea920SConor Dooleytitle: Last Level Cache Controller 8*dc8ea920SConor Dooley 9*dc8ea920SConor Dooleymaintainers: 10*dc8ea920SConor Dooley - Rishabh Bhatnagar <rishabhb@codeaurora.org> 11*dc8ea920SConor Dooley - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> 12*dc8ea920SConor Dooley 13*dc8ea920SConor Dooleydescription: | 14*dc8ea920SConor Dooley LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, 15*dc8ea920SConor Dooley that can be shared by multiple clients. Clients here are different cores in the 16*dc8ea920SConor Dooley SoC, the idea is to minimize the local caches at the clients and migrate to 17*dc8ea920SConor Dooley common pool of memory. Cache memory is divided into partitions called slices 18*dc8ea920SConor Dooley which are assigned to clients. Clients can query the slice details, activate 19*dc8ea920SConor Dooley and deactivate them. 20*dc8ea920SConor Dooley 21*dc8ea920SConor Dooleyproperties: 22*dc8ea920SConor Dooley compatible: 23*dc8ea920SConor Dooley enum: 24*dc8ea920SConor Dooley - qcom,sc7180-llcc 25*dc8ea920SConor Dooley - qcom,sc7280-llcc 26*dc8ea920SConor Dooley - qcom,sc8180x-llcc 27*dc8ea920SConor Dooley - qcom,sc8280xp-llcc 28*dc8ea920SConor Dooley - qcom,sdm845-llcc 29*dc8ea920SConor Dooley - qcom,sm6350-llcc 30*dc8ea920SConor Dooley - qcom,sm8150-llcc 31*dc8ea920SConor Dooley - qcom,sm8250-llcc 32*dc8ea920SConor Dooley - qcom,sm8350-llcc 33*dc8ea920SConor Dooley - qcom,sm8450-llcc 34*dc8ea920SConor Dooley - qcom,sm8550-llcc 35*dc8ea920SConor Dooley 36*dc8ea920SConor Dooley reg: 37*dc8ea920SConor Dooley items: 38*dc8ea920SConor Dooley - description: LLCC base register region 39*dc8ea920SConor Dooley - description: LLCC broadcast base register region 40*dc8ea920SConor Dooley 41*dc8ea920SConor Dooley reg-names: 42*dc8ea920SConor Dooley items: 43*dc8ea920SConor Dooley - const: llcc_base 44*dc8ea920SConor Dooley - const: llcc_broadcast_base 45*dc8ea920SConor Dooley 46*dc8ea920SConor Dooley interrupts: 47*dc8ea920SConor Dooley maxItems: 1 48*dc8ea920SConor Dooley 49*dc8ea920SConor Dooleyrequired: 50*dc8ea920SConor Dooley - compatible 51*dc8ea920SConor Dooley - reg 52*dc8ea920SConor Dooley - reg-names 53*dc8ea920SConor Dooley 54*dc8ea920SConor DooleyadditionalProperties: false 55*dc8ea920SConor Dooley 56*dc8ea920SConor Dooleyexamples: 57*dc8ea920SConor Dooley - | 58*dc8ea920SConor Dooley #include <dt-bindings/interrupt-controller/arm-gic.h> 59*dc8ea920SConor Dooley 60*dc8ea920SConor Dooley system-cache-controller@1100000 { 61*dc8ea920SConor Dooley compatible = "qcom,sdm845-llcc"; 62*dc8ea920SConor Dooley reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; 63*dc8ea920SConor Dooley reg-names = "llcc_base", "llcc_broadcast_base"; 64*dc8ea920SConor Dooley interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 65*dc8ea920SConor Dooley }; 66