1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments interconnect target module binding
8
9maintainers:
10  - Tony Lindgren <tony@atomide.com>
11
12description:
13  Texas Instruments SoCs can have a generic interconnect target module
14  for devices connected to various interconnects such as L3 interconnect
15  using Arteris NoC, and L4 interconnect using Sonics s3220. This module
16  is mostly used for interaction between module and Power, Reset and Clock
17  Manager PRCM. It participates in the OCP Disconnect Protocol, but other
18  than that it is mostly independent of the interconnect.
19
20  Each interconnect target module can have one or more devices connected to
21  it. There is a set of control registers for managing the interconnect target
22  module clocks, idle modes and interconnect level resets.
23
24  The interconnect target module control registers are sprinkled into the
25  unused register address space of the first child device IP block managed by
26  the interconnect target module. Typically the register names are REVISION,
27  SYSCONFIG and SYSSTATUS.
28
29properties:
30  $nodename:
31    pattern: "^target-module(@[0-9a-f]+)?$"
32
33  compatible:
34    oneOf:
35      - items:
36          - enum:
37              - ti,sysc-omap2
38              - ti,sysc-omap2
39              - ti,sysc-omap4
40              - ti,sysc-omap4-simple
41              - ti,sysc-omap2-timer
42              - ti,sysc-omap4-timer
43              - ti,sysc-omap3430-sr
44              - ti,sysc-omap3630-sr
45              - ti,sysc-omap4-sr
46              - ti,sysc-omap3-sham
47              - ti,sysc-omap-aes
48              - ti,sysc-mcasp
49              - ti,sysc-dra7-mcasp
50              - ti,sysc-usb-host-fs
51              - ti,sysc-dra7-mcan
52              - ti,sysc-pruss
53          - const: ti,sysc
54      - items:
55          - const: ti,sysc
56
57  reg:
58    description:
59      Interconnect target module control registers consisting of
60      REVISION, SYSCONFIG and SYSSTATUS registers as defined in the
61      Technical Reference Manual for the SoC.
62    minItems: 1
63    maxItems: 3
64
65  reg-names:
66    description:
67      Interconnect target module control register names consisting
68      of "rev", "sysc" and "syss".
69    oneOf:
70      - minItems: 1
71        items:
72          - const: rev
73          - const: sysc
74          - const: syss
75      - items:
76          - const: rev
77          - const: syss
78      - enum: [ sysc, syss ]
79
80  power-domains:
81    description: Target module power domain if available.
82    maxItems: 1
83
84  clocks:
85    description:
86      Target module clocks consisting of one functional clock, one
87      interface clock, and up to 8 module specific optional clocks.
88      Some modules may have only the functional clock, and some have
89      no configurable clocks.
90    minItems: 1
91    maxItems: 4
92
93  clock-names:
94    description:
95      Target module clock names like "fck", "ick", "optck1", "optck2"
96      if the clocks are configurable.
97    oneOf:
98      - enum: [ ick, fck, sys_clk ]
99      - items:
100          - const: fck
101          - enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ]
102      - items:
103          - const: fck
104          - const: phy-clk
105          - const: phy-clk-div
106      - items:
107          - const: fck
108          - const: hdmi_clk
109          - const: sys_clk
110          - const: tv_clk
111      - items:
112          - const: fck
113          - const: ahclkx
114          - const: ahclkr
115
116  resets:
117    description:
118      Target module reset bit in the RSTCTRL register if wired for the module.
119      Note that the other reset bits should be mapped for the child device
120      driver to use.
121    maxItems: 1
122
123  reset-names:
124    description:
125      Target module reset names in the RSTCTRL register, typically named
126      "rstctrl" if only one reset bit is wired for the module.
127    items:
128      - const: rstctrl
129
130  '#address-cells':
131    enum: [ 1, 2 ]
132
133  '#size-cells':
134    enum: [ 1, 2 ]
135
136  ranges: true
137
138  dma-ranges: true
139
140  ti,sysc-mask:
141    description: Mask of supported register bits for the SYSCONFIG register
142    $ref: /schemas/types.yaml#/definitions/uint32
143
144  ti,sysc-midle:
145    description: List of hardware supported idle modes
146    $ref: /schemas/types.yaml#/definitions/uint32-array
147
148  ti,sysc-sidle:
149    description: List of hardware supported idle modes
150    $ref: /schemas/types.yaml#/definitions/uint32-array
151
152  ti,syss-mask:
153    description: Mask of supported register bits for the SYSSTATUS register
154    $ref: /schemas/types.yaml#/definitions/uint32
155
156  ti,sysc-delay-us:
157    description: Delay needed after OCP softreset before accessing SYCONFIG
158    default: 0
159    minimum: 0
160    maximum: 2
161
162  ti,no-reset-on-init:
163    description: Interconnect target module shall not be reset at init
164    type: boolean
165
166  ti,no-idle-on-init:
167    description: Interconnect target module shall not be idled at init
168    type: boolean
169
170  ti,no-idle:
171    description: Interconnect target module shall not be idled
172    type: boolean
173
174  ti,hwmods:
175    description: Interconnect module name to use with legacy hwmod data
176    $ref: /schemas/types.yaml#/definitions/string
177    deprecated: true
178
179required:
180  - compatible
181  - '#address-cells'
182  - '#size-cells'
183  - ranges
184
185additionalProperties:
186  type: object
187
188examples:
189  - |
190    #include <dt-bindings/bus/ti-sysc.h>
191    #include <dt-bindings/clock/omap4.h>
192
193    target-module@2b000 {
194        compatible = "ti,sysc-omap2", "ti,sysc";
195        ti,hwmods = "usb_otg_hs";
196        reg = <0x2b400 0x4>,
197              <0x2b404 0x4>,
198              <0x2b408 0x4>;
199        reg-names = "rev", "sysc", "syss";
200        clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
201        clock-names = "fck";
202        ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
203                         SYSC_OMAP2_SOFTRESET |
204                         SYSC_OMAP2_AUTOIDLE)>;
205        ti,sysc-midle = <SYSC_IDLE_FORCE>,
206                        <SYSC_IDLE_NO>,
207                        <SYSC_IDLE_SMART>;
208        ti,sysc-sidle = <SYSC_IDLE_FORCE>,
209                        <SYSC_IDLE_NO>,
210                        <SYSC_IDLE_SMART>,
211                        <SYSC_IDLE_SMART_WKUP>;
212        ti,syss-mask = <1>;
213        #address-cells = <1>;
214        #size-cells = <1>;
215        ranges = <0 0x2b000 0x1000>;
216    };
217