17f44205eSMasahiro Yamada# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 27f44205eSMasahiro Yamada%YAML 1.2 37f44205eSMasahiro Yamada--- 47f44205eSMasahiro Yamada$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml# 57f44205eSMasahiro Yamada$schema: http://devicetree.org/meta-schemas/core.yaml# 67f44205eSMasahiro Yamada 77f44205eSMasahiro Yamadatitle: UniPhier System Bus 87f44205eSMasahiro Yamada 97f44205eSMasahiro Yamadadescription: | 107f44205eSMasahiro Yamada The UniPhier System Bus is an external bus that connects on-board devices to 117f44205eSMasahiro Yamada the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and 127f44205eSMasahiro Yamada some control signals. It supports up to 8 banks (chip selects). 137f44205eSMasahiro Yamada 147f44205eSMasahiro Yamada Before any access to the bus, the bus controller must be configured; the bus 157f44205eSMasahiro Yamada controller registers provide the control for the translation from the offset 167f44205eSMasahiro Yamada within each bank to the CPU-viewed address. The needed setup includes the 177f44205eSMasahiro Yamada base address, the size of each bank. Optionally, some timing parameters can 187f44205eSMasahiro Yamada be optimized for faster bus access. 197f44205eSMasahiro Yamada 207f44205eSMasahiro Yamadamaintainers: 217f44205eSMasahiro Yamada - Masahiro Yamada <yamada.masahiro@socionext.com> 227f44205eSMasahiro Yamada 237f44205eSMasahiro Yamadaproperties: 247f44205eSMasahiro Yamada compatible: 257f44205eSMasahiro Yamada const: socionext,uniphier-system-bus 267f44205eSMasahiro Yamada 277f44205eSMasahiro Yamada reg: 287f44205eSMasahiro Yamada maxItems: 1 297f44205eSMasahiro Yamada 307f44205eSMasahiro Yamada "#address-cells": 317f44205eSMasahiro Yamada description: | 327f44205eSMasahiro Yamada The first cell is the bank number (chip select). 337f44205eSMasahiro Yamada The second cell is the address offset within the bank. 347f44205eSMasahiro Yamada const: 2 357f44205eSMasahiro Yamada 367f44205eSMasahiro Yamada "#size-cells": 377f44205eSMasahiro Yamada const: 1 387f44205eSMasahiro Yamada 397f44205eSMasahiro Yamada ranges: 407f44205eSMasahiro Yamada description: | 417f44205eSMasahiro Yamada Provide address translation from the System Bus to the parent bus. 427f44205eSMasahiro Yamada 437f44205eSMasahiro Yamada Note: 447f44205eSMasahiro Yamada The address region(s) that can be assigned for the System Bus is 457f44205eSMasahiro Yamada implementation defined. Some SoCs can use 0x00000000-0x0fffffff and 467f44205eSMasahiro Yamada 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff. 477f44205eSMasahiro Yamada There might be additional limitations depending on SoCs and the boot mode. 487f44205eSMasahiro Yamada The address translation is arbitrary as long as the banks are assigned in 497f44205eSMasahiro Yamada the supported address space with the required alignment and they do not 507f44205eSMasahiro Yamada overlap one another. 517f44205eSMasahiro Yamada 527f44205eSMasahiro Yamada For example, it is possible to map: 537f44205eSMasahiro Yamada bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff 547f44205eSMasahiro Yamada It is also possible to map: 557f44205eSMasahiro Yamada bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff 567f44205eSMasahiro Yamada There is no reason to stick to a particular translation mapping, but the 577f44205eSMasahiro Yamada "ranges" property should provide a "reasonable" default that is known to 587f44205eSMasahiro Yamada work. The software should initialize the bus controller according to it. 597f44205eSMasahiro Yamada 607f44205eSMasahiro Yamadarequired: 617f44205eSMasahiro Yamada - compatible 627f44205eSMasahiro Yamada - reg 637f44205eSMasahiro Yamada - "#address-cells" 647f44205eSMasahiro Yamada - "#size-cells" 657f44205eSMasahiro Yamada - ranges 667f44205eSMasahiro Yamada 677f44205eSMasahiro Yamadaexamples: 687f44205eSMasahiro Yamada - | 697f44205eSMasahiro Yamada // In this example, 707f44205eSMasahiro Yamada // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and 717f44205eSMasahiro Yamada // mapped to 0x43f00000 of the parent bus. 727f44205eSMasahiro Yamada // - the UART device is connected at the offset 0x00200000 of CS5 and 737f44205eSMasahiro Yamada // mapped to 0x46200000 of the parent bus. 747f44205eSMasahiro Yamada 7539eca91cSMasahiro Yamada system-bus@58c00000 { 767f44205eSMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 777f44205eSMasahiro Yamada reg = <0x58c00000 0x400>; 787f44205eSMasahiro Yamada #address-cells = <2>; 797f44205eSMasahiro Yamada #size-cells = <1>; 807f44205eSMasahiro Yamada ranges = <1 0x00000000 0x42000000 0x02000000>, 817f44205eSMasahiro Yamada <5 0x00000000 0x46000000 0x01000000>; 827f44205eSMasahiro Yamada 830fb24d1eSMasahiro Yamada ethernet@1,1f00000 { 847f44205eSMasahiro Yamada compatible = "smsc,lan9115"; 857f44205eSMasahiro Yamada reg = <1 0x01f00000 0x1000>; 867f44205eSMasahiro Yamada interrupts = <0 48 4>; 877f44205eSMasahiro Yamada phy-mode = "mii"; 887f44205eSMasahiro Yamada }; 897f44205eSMasahiro Yamada 900fb24d1eSMasahiro Yamada serial@5,200000 { 917f44205eSMasahiro Yamada compatible = "ns16550a"; 927f44205eSMasahiro Yamada reg = <5 0x00200000 0x20>; 937f44205eSMasahiro Yamada interrupts = <0 49 4>; 947f44205eSMasahiro Yamada clock-frequency = <12288000>; 957f44205eSMasahiro Yamada }; 967f44205eSMasahiro Yamada }; 97