1*0b9fe9b7SMichael Srba# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*0b9fe9b7SMichael Srba%YAML 1.2 3*0b9fe9b7SMichael Srba--- 4*0b9fe9b7SMichael Srba$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# 5*0b9fe9b7SMichael Srba$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0b9fe9b7SMichael Srba 7*0b9fe9b7SMichael Srbatitle: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs 8*0b9fe9b7SMichael Srba 9*0b9fe9b7SMichael Srbamaintainers: 10*0b9fe9b7SMichael Srba - Michael Srba <Michael.Srba@seznam.cz> 11*0b9fe9b7SMichael Srba 12*0b9fe9b7SMichael Srbadescription: | 13*0b9fe9b7SMichael Srba This binding describes the dependencies (clocks, resets, power domains) which 14*0b9fe9b7SMichael Srba need to be turned on in a sequence before communication over the AHB bus 15*0b9fe9b7SMichael Srba becomes possible. 16*0b9fe9b7SMichael Srba 17*0b9fe9b7SMichael Srba Additionally, the reg property is used to pass to the driver the location of 18*0b9fe9b7SMichael Srba two sadly undocumented registers which need to be poked as part of the sequence. 19*0b9fe9b7SMichael Srba 20*0b9fe9b7SMichael Srba The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart 21*0b9fe9b7SMichael Srba controllers, a hexagon core, and a clock controller which provides clocks for 22*0b9fe9b7SMichael Srba the above. 23*0b9fe9b7SMichael Srba 24*0b9fe9b7SMichael Srbaproperties: 25*0b9fe9b7SMichael Srba compatible: 26*0b9fe9b7SMichael Srba items: 27*0b9fe9b7SMichael Srba - const: qcom,msm8998-ssc-block-bus 28*0b9fe9b7SMichael Srba - const: qcom,ssc-block-bus 29*0b9fe9b7SMichael Srba 30*0b9fe9b7SMichael Srba reg: 31*0b9fe9b7SMichael Srba description: | 32*0b9fe9b7SMichael Srba Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1 33*0b9fe9b7SMichael Srba registers 34*0b9fe9b7SMichael Srba minItems: 2 35*0b9fe9b7SMichael Srba maxItems: 2 36*0b9fe9b7SMichael Srba 37*0b9fe9b7SMichael Srba reg-names: 38*0b9fe9b7SMichael Srba items: 39*0b9fe9b7SMichael Srba - const: mpm_sscaon_config0 40*0b9fe9b7SMichael Srba - const: mpm_sscaon_config1 41*0b9fe9b7SMichael Srba 42*0b9fe9b7SMichael Srba '#address-cells': 43*0b9fe9b7SMichael Srba enum: [ 1, 2 ] 44*0b9fe9b7SMichael Srba 45*0b9fe9b7SMichael Srba '#size-cells': 46*0b9fe9b7SMichael Srba enum: [ 1, 2 ] 47*0b9fe9b7SMichael Srba 48*0b9fe9b7SMichael Srba ranges: true 49*0b9fe9b7SMichael Srba 50*0b9fe9b7SMichael Srba clocks: 51*0b9fe9b7SMichael Srba minItems: 6 52*0b9fe9b7SMichael Srba maxItems: 6 53*0b9fe9b7SMichael Srba 54*0b9fe9b7SMichael Srba clock-names: 55*0b9fe9b7SMichael Srba items: 56*0b9fe9b7SMichael Srba - const: xo 57*0b9fe9b7SMichael Srba - const: aggre2 58*0b9fe9b7SMichael Srba - const: gcc_im_sleep 59*0b9fe9b7SMichael Srba - const: aggre2_north 60*0b9fe9b7SMichael Srba - const: ssc_xo 61*0b9fe9b7SMichael Srba - const: ssc_ahbs 62*0b9fe9b7SMichael Srba 63*0b9fe9b7SMichael Srba power-domains: 64*0b9fe9b7SMichael Srba description: Power domain phandles for the ssc_cx and ssc_mx power domains 65*0b9fe9b7SMichael Srba minItems: 2 66*0b9fe9b7SMichael Srba maxItems: 2 67*0b9fe9b7SMichael Srba 68*0b9fe9b7SMichael Srba power-domain-names: 69*0b9fe9b7SMichael Srba items: 70*0b9fe9b7SMichael Srba - const: ssc_cx 71*0b9fe9b7SMichael Srba - const: ssc_mx 72*0b9fe9b7SMichael Srba 73*0b9fe9b7SMichael Srba resets: 74*0b9fe9b7SMichael Srba description: | 75*0b9fe9b7SMichael Srba Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the 76*0b9fe9b7SMichael Srba branch control register associated with the ssc_xo and ssc_ahbs clocks) 77*0b9fe9b7SMichael Srba minItems: 2 78*0b9fe9b7SMichael Srba maxItems: 2 79*0b9fe9b7SMichael Srba 80*0b9fe9b7SMichael Srba reset-names: 81*0b9fe9b7SMichael Srba items: 82*0b9fe9b7SMichael Srba - const: ssc_reset 83*0b9fe9b7SMichael Srba - const: ssc_bcr 84*0b9fe9b7SMichael Srba 85*0b9fe9b7SMichael Srba qcom,halt-regs: 86*0b9fe9b7SMichael Srba $ref: /schemas/types.yaml#/definitions/phandle-array 87*0b9fe9b7SMichael Srba description: describes how to locate the ssc AXI halt register 88*0b9fe9b7SMichael Srba items: 89*0b9fe9b7SMichael Srba - items: 90*0b9fe9b7SMichael Srba - description: Phandle reference to a syscon representing TCSR 91*0b9fe9b7SMichael Srba - description: offset for the ssc AXI halt register 92*0b9fe9b7SMichael Srba 93*0b9fe9b7SMichael Srbarequired: 94*0b9fe9b7SMichael Srba - compatible 95*0b9fe9b7SMichael Srba - reg 96*0b9fe9b7SMichael Srba - reg-names 97*0b9fe9b7SMichael Srba - '#address-cells' 98*0b9fe9b7SMichael Srba - '#size-cells' 99*0b9fe9b7SMichael Srba - ranges 100*0b9fe9b7SMichael Srba - clocks 101*0b9fe9b7SMichael Srba - clock-names 102*0b9fe9b7SMichael Srba - power-domains 103*0b9fe9b7SMichael Srba - power-domain-names 104*0b9fe9b7SMichael Srba - resets 105*0b9fe9b7SMichael Srba - reset-names 106*0b9fe9b7SMichael Srba - qcom,halt-regs 107*0b9fe9b7SMichael Srba 108*0b9fe9b7SMichael SrbaadditionalProperties: 109*0b9fe9b7SMichael Srba type: object 110*0b9fe9b7SMichael Srba 111*0b9fe9b7SMichael Srbaexamples: 112*0b9fe9b7SMichael Srba - | 113*0b9fe9b7SMichael Srba #include <dt-bindings/clock/qcom,gcc-msm8998.h> 114*0b9fe9b7SMichael Srba #include <dt-bindings/clock/qcom,rpmcc.h> 115*0b9fe9b7SMichael Srba #include <dt-bindings/power/qcom-rpmpd.h> 116*0b9fe9b7SMichael Srba 117*0b9fe9b7SMichael Srba soc { 118*0b9fe9b7SMichael Srba #address-cells = <1>; 119*0b9fe9b7SMichael Srba #size-cells = <1>; 120*0b9fe9b7SMichael Srba 121*0b9fe9b7SMichael Srba // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; 122*0b9fe9b7SMichael Srba ssc_ahb_slave: bus@10ac008 { 123*0b9fe9b7SMichael Srba #address-cells = <1>; 124*0b9fe9b7SMichael Srba #size-cells = <1>; 125*0b9fe9b7SMichael Srba ranges; 126*0b9fe9b7SMichael Srba 127*0b9fe9b7SMichael Srba compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus"; 128*0b9fe9b7SMichael Srba reg = <0x10ac008 0x4>, <0x10ac010 0x4>; 129*0b9fe9b7SMichael Srba reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; 130*0b9fe9b7SMichael Srba 131*0b9fe9b7SMichael Srba clocks = <&xo>, 132*0b9fe9b7SMichael Srba <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 133*0b9fe9b7SMichael Srba <&gcc GCC_IM_SLEEP>, 134*0b9fe9b7SMichael Srba <&gcc AGGRE2_SNOC_NORTH_AXI>, 135*0b9fe9b7SMichael Srba <&gcc SSC_XO>, 136*0b9fe9b7SMichael Srba <&gcc SSC_CNOC_AHBS_CLK>; 137*0b9fe9b7SMichael Srba clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; 138*0b9fe9b7SMichael Srba 139*0b9fe9b7SMichael Srba resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; 140*0b9fe9b7SMichael Srba reset-names = "ssc_reset", "ssc_bcr"; 141*0b9fe9b7SMichael Srba 142*0b9fe9b7SMichael Srba power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; 143*0b9fe9b7SMichael Srba power-domain-names = "ssc_cx", "ssc_mx"; 144*0b9fe9b7SMichael Srba 145*0b9fe9b7SMichael Srba qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; 146*0b9fe9b7SMichael Srba }; 147*0b9fe9b7SMichael Srba }; 148