1*e36f9381SSameer Pujar# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*e36f9381SSameer Pujar%YAML 1.2 3*e36f9381SSameer Pujar--- 4*e36f9381SSameer Pujar$id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml# 5*e36f9381SSameer Pujar$schema: http://devicetree.org/meta-schemas/core.yaml# 6*e36f9381SSameer Pujar 7*e36f9381SSameer Pujartitle: NVIDIA Tegra ACONNECT Bus 8*e36f9381SSameer Pujar 9*e36f9381SSameer Pujardescription: | 10*e36f9381SSameer Pujar The Tegra ACONNECT bus is an AXI switch which is used to connnect various 11*e36f9381SSameer Pujar components inside the Audio Processing Engine (APE). All CPU accesses to 12*e36f9381SSameer Pujar the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All 13*e36f9381SSameer Pujar devices accessed via the ACONNNECT are described by child-nodes. 14*e36f9381SSameer Pujar 15*e36f9381SSameer Pujarmaintainers: 16*e36f9381SSameer Pujar - Jon Hunter <jonathanh@nvidia.com> 17*e36f9381SSameer Pujar 18*e36f9381SSameer Pujarproperties: 19*e36f9381SSameer Pujar compatible: 20*e36f9381SSameer Pujar oneOf: 21*e36f9381SSameer Pujar - const: nvidia,tegra210-aconnect 22*e36f9381SSameer Pujar - items: 23*e36f9381SSameer Pujar - enum: 24*e36f9381SSameer Pujar - nvidia,tegra186-aconnect 25*e36f9381SSameer Pujar - nvidia,tegra194-aconnect 26*e36f9381SSameer Pujar - const: nvidia,tegra210-aconnect 27*e36f9381SSameer Pujar 28*e36f9381SSameer Pujar clocks: 29*e36f9381SSameer Pujar items: 30*e36f9381SSameer Pujar - description: Must contain the entry for APE clock 31*e36f9381SSameer Pujar - description: Must contain the entry for APE interface clock 32*e36f9381SSameer Pujar 33*e36f9381SSameer Pujar clock-names: 34*e36f9381SSameer Pujar items: 35*e36f9381SSameer Pujar - const: ape 36*e36f9381SSameer Pujar - const: apb2ape 37*e36f9381SSameer Pujar 38*e36f9381SSameer Pujar power-domains: 39*e36f9381SSameer Pujar maxItems: 1 40*e36f9381SSameer Pujar 41*e36f9381SSameer Pujar "#address-cells": 42*e36f9381SSameer Pujar const: 1 43*e36f9381SSameer Pujar 44*e36f9381SSameer Pujar "#size-cells": 45*e36f9381SSameer Pujar const: 1 46*e36f9381SSameer Pujar 47*e36f9381SSameer Pujar ranges: true 48*e36f9381SSameer Pujar 49*e36f9381SSameer PujarpatternProperties: 50*e36f9381SSameer Pujar "@[0-9a-f]+$": 51*e36f9381SSameer Pujar type: object 52*e36f9381SSameer Pujar 53*e36f9381SSameer Pujarrequired: 54*e36f9381SSameer Pujar - compatible 55*e36f9381SSameer Pujar - clocks 56*e36f9381SSameer Pujar - clock-names 57*e36f9381SSameer Pujar - power-domains 58*e36f9381SSameer Pujar - "#address-cells" 59*e36f9381SSameer Pujar - "#size-cells" 60*e36f9381SSameer Pujar - ranges 61*e36f9381SSameer Pujar 62*e36f9381SSameer PujaradditionalProperties: false 63*e36f9381SSameer Pujar 64*e36f9381SSameer Pujarexamples: 65*e36f9381SSameer Pujar - | 66*e36f9381SSameer Pujar #include<dt-bindings/clock/tegra210-car.h> 67*e36f9381SSameer Pujar 68*e36f9381SSameer Pujar aconnect@702c0000 { 69*e36f9381SSameer Pujar compatible = "nvidia,tegra210-aconnect"; 70*e36f9381SSameer Pujar clocks = <&tegra_car TEGRA210_CLK_APE>, 71*e36f9381SSameer Pujar <&tegra_car TEGRA210_CLK_APB2APE>; 72*e36f9381SSameer Pujar clock-names = "ape", "apb2ape"; 73*e36f9381SSameer Pujar power-domains = <&pd_audio>; 74*e36f9381SSameer Pujar 75*e36f9381SSameer Pujar #address-cells = <1>; 76*e36f9381SSameer Pujar #size-cells = <1>; 77*e36f9381SSameer Pujar ranges = <0x702c0000 0x702c0000 0x00040000>; 78*e36f9381SSameer Pujar 79*e36f9381SSameer Pujar // Child device nodes follow ... 80*e36f9381SSameer Pujar }; 81*e36f9381SSameer Pujar 82*e36f9381SSameer Pujar... 83