1*5d16dcd2SCorentin Labbe# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*5d16dcd2SCorentin Labbe%YAML 1.2 3*5d16dcd2SCorentin Labbe--- 4*5d16dcd2SCorentin Labbe$id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml# 5*5d16dcd2SCorentin Labbe$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5d16dcd2SCorentin Labbe 7*5d16dcd2SCorentin Labbetitle: Cortina Systems Gemini SATA Bridge 8*5d16dcd2SCorentin Labbe 9*5d16dcd2SCorentin Labbemaintainers: 10*5d16dcd2SCorentin Labbe - Linus Walleij <linus.walleij@linaro.org> 11*5d16dcd2SCorentin Labbe 12*5d16dcd2SCorentin Labbedescription: | 13*5d16dcd2SCorentin Labbe The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that 14*5d16dcd2SCorentin Labbe takes two Faraday Technology FTIDE010 PATA controllers and bridges 15*5d16dcd2SCorentin Labbe them in different configurations to two SATA ports. 16*5d16dcd2SCorentin Labbe 17*5d16dcd2SCorentin Labbeproperties: 18*5d16dcd2SCorentin Labbe compatible: 19*5d16dcd2SCorentin Labbe const: cortina,gemini-sata-bridge 20*5d16dcd2SCorentin Labbe 21*5d16dcd2SCorentin Labbe reg: 22*5d16dcd2SCorentin Labbe maxItems: 1 23*5d16dcd2SCorentin Labbe 24*5d16dcd2SCorentin Labbe resets: 25*5d16dcd2SCorentin Labbe minItems: 2 26*5d16dcd2SCorentin Labbe maxItems: 2 27*5d16dcd2SCorentin Labbe description: phandles to the reset lines for both SATA bridges 28*5d16dcd2SCorentin Labbe 29*5d16dcd2SCorentin Labbe reset-names: 30*5d16dcd2SCorentin Labbe items: 31*5d16dcd2SCorentin Labbe - const: sata0 32*5d16dcd2SCorentin Labbe - const: sata1 33*5d16dcd2SCorentin Labbe 34*5d16dcd2SCorentin Labbe clocks: 35*5d16dcd2SCorentin Labbe minItems: 2 36*5d16dcd2SCorentin Labbe maxItems: 2 37*5d16dcd2SCorentin Labbe description: phandles to the compulsory peripheral clocks 38*5d16dcd2SCorentin Labbe 39*5d16dcd2SCorentin Labbe clock-names: 40*5d16dcd2SCorentin Labbe items: 41*5d16dcd2SCorentin Labbe - const: SATA0_PCLK 42*5d16dcd2SCorentin Labbe - const: SATA1_PCLK 43*5d16dcd2SCorentin Labbe 44*5d16dcd2SCorentin Labbe syscon: 45*5d16dcd2SCorentin Labbe $ref: /schemas/types.yaml#/definitions/phandle 46*5d16dcd2SCorentin Labbe description: a phandle to the global Gemini system controller 47*5d16dcd2SCorentin Labbe 48*5d16dcd2SCorentin Labbe cortina,gemini-ata-muxmode: 49*5d16dcd2SCorentin Labbe $ref: /schemas/types.yaml#/definitions/uint32 50*5d16dcd2SCorentin Labbe enum: 51*5d16dcd2SCorentin Labbe - 0 52*5d16dcd2SCorentin Labbe - 1 53*5d16dcd2SCorentin Labbe - 2 54*5d16dcd2SCorentin Labbe - 3 55*5d16dcd2SCorentin Labbe description: | 56*5d16dcd2SCorentin Labbe Tell the desired multiplexing mode for the ATA controller and SATA 57*5d16dcd2SCorentin Labbe bridges. 58*5d16dcd2SCorentin Labbe Mode 0: ata0 master <-> sata0 59*5d16dcd2SCorentin Labbe ata1 master <-> sata1 60*5d16dcd2SCorentin Labbe ata0 slave interface brought out on IDE pads 61*5d16dcd2SCorentin Labbe Mode 1: ata0 master <-> sata0 62*5d16dcd2SCorentin Labbe ata1 master <-> sata1 63*5d16dcd2SCorentin Labbe ata1 slave interface brought out on IDE pads 64*5d16dcd2SCorentin Labbe Mode 2: ata1 master <-> sata1 65*5d16dcd2SCorentin Labbe ata1 slave <-> sata0 66*5d16dcd2SCorentin Labbe ata0 master and slave interfaces brought out on IDE pads 67*5d16dcd2SCorentin Labbe Mode 3: ata0 master <-> sata0 68*5d16dcd2SCorentin Labbe ata0 slave <-> sata1 69*5d16dcd2SCorentin Labbe ata1 master and slave interfaces brought out on IDE pads 70*5d16dcd2SCorentin Labbe 71*5d16dcd2SCorentin Labbe cortina,gemini-enable-ide-pins: 72*5d16dcd2SCorentin Labbe type: boolean 73*5d16dcd2SCorentin Labbe description: Enables the PATA to IDE connection. 74*5d16dcd2SCorentin Labbe The muxmode setting decides whether ATA0 or ATA1 is brought out, 75*5d16dcd2SCorentin Labbe and whether master, slave or both interfaces get brought out. 76*5d16dcd2SCorentin Labbe 77*5d16dcd2SCorentin Labbe cortina,gemini-enable-sata-bridge: 78*5d16dcd2SCorentin Labbe type: boolean 79*5d16dcd2SCorentin Labbe description: Enables the PATA to SATA bridge inside the Gemnini SoC. 80*5d16dcd2SCorentin Labbe The Muxmode decides what PATA blocks will be muxed out and how. 81*5d16dcd2SCorentin Labbe 82*5d16dcd2SCorentin Labberequired: 83*5d16dcd2SCorentin Labbe - clocks 84*5d16dcd2SCorentin Labbe - clock-names 85*5d16dcd2SCorentin Labbe - cortina,gemini-ata-muxmode 86*5d16dcd2SCorentin Labbe - resets 87*5d16dcd2SCorentin Labbe - reset-names 88*5d16dcd2SCorentin Labbe - compatible 89*5d16dcd2SCorentin Labbe - reg 90*5d16dcd2SCorentin Labbe - syscon 91*5d16dcd2SCorentin Labbe 92*5d16dcd2SCorentin LabbeadditionalProperties: false 93*5d16dcd2SCorentin Labbe 94*5d16dcd2SCorentin Labbeexamples: 95*5d16dcd2SCorentin Labbe - | 96*5d16dcd2SCorentin Labbe #include <dt-bindings/clock/cortina,gemini-clock.h> 97*5d16dcd2SCorentin Labbe sata@46000000 { 98*5d16dcd2SCorentin Labbe compatible = "cortina,gemini-sata-bridge"; 99*5d16dcd2SCorentin Labbe reg = <0x46000000 0x100>; 100*5d16dcd2SCorentin Labbe resets = <&rcon 26>, <&rcon 27>; 101*5d16dcd2SCorentin Labbe reset-names = "sata0", "sata1"; 102*5d16dcd2SCorentin Labbe clocks = <&gcc GEMINI_CLK_GATE_SATA0>, 103*5d16dcd2SCorentin Labbe <&gcc GEMINI_CLK_GATE_SATA1>; 104*5d16dcd2SCorentin Labbe clock-names = "SATA0_PCLK", "SATA1_PCLK"; 105*5d16dcd2SCorentin Labbe syscon = <&syscon>; 106*5d16dcd2SCorentin Labbe cortina,gemini-ata-muxmode = <3>; 107*5d16dcd2SCorentin Labbe cortina,gemini-enable-ide-pins; 108*5d16dcd2SCorentin Labbe cortina,gemini-enable-sata-bridge; 109*5d16dcd2SCorentin Labbe }; 110