1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Common Properties for Serial ATA AHCI controllers
8
9maintainers:
10  - Hans de Goede <hdegoede@redhat.com>
11  - Damien Le Moal <damien.lemoal@opensource.wdc.com>
12
13description:
14  This document defines device tree properties for a common AHCI SATA
15  controller implementation. It's hardware interface is supposed to
16  conform to the technical standard defined by Intel (see Serial ATA
17  Advanced Host Controller Interface specification for details). The
18  document doesn't constitute a DT-node binding by itself but merely
19  defines a set of common properties for the AHCI-compatible devices.
20
21select: false
22
23allOf:
24  - $ref: sata-common.yaml#
25
26properties:
27  reg:
28    description:
29      Generic AHCI registers space conforming to the Serial ATA AHCI
30      specification.
31
32  reg-names:
33    description: CSR space IDs
34
35  interrupts:
36    description:
37      Generic AHCI state change interrupt. Can be implemented either as a
38      single line attached to the controller or as a set of the signals
39      indicating the particular port events.
40
41  ahci-supply:
42    description: Power regulator for AHCI controller
43
44  target-supply:
45    description: Power regulator for SATA target device
46
47  phy-supply:
48    description: Power regulator for SATA PHY
49
50  phys:
51    description: Reference to the SATA PHY node
52    maxItems: 1
53
54  phy-names:
55    maxItems: 1
56
57  ports-implemented:
58    $ref: '/schemas/types.yaml#/definitions/uint32'
59    description:
60      Mask that indicates which ports the HBA supports. Useful if PI is not
61      programmed by the BIOS, which is true for some embedded SoC's.
62    maximum: 0x1f
63
64patternProperties:
65  "^sata-port@[0-9a-f]+$":
66    $ref: '#/$defs/ahci-port'
67    description:
68      It is optionally possible to describe the ports as sub-nodes so
69      to enable each port independently when dealing with multiple PHYs.
70
71required:
72  - reg
73  - interrupts
74
75additionalProperties: true
76
77$defs:
78  ahci-port:
79    $ref: /schemas/ata/sata-common.yaml#/$defs/sata-port
80
81    properties:
82      reg:
83        description: AHCI SATA port identifier
84        maxItems: 1
85
86      phys:
87        description: Individual AHCI SATA port PHY
88        maxItems: 1
89
90      phy-names:
91        description: AHCI SATA port PHY ID
92        maxItems: 1
93
94      target-supply:
95        description: Power regulator for SATA port target device
96
97    required:
98      - reg
99
100...
101