1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Tegra Power Management Controller (PMC) 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 enum: 16 - nvidia,tegra20-pmc 17 - nvidia,tegra20-pmc 18 - nvidia,tegra30-pmc 19 - nvidia,tegra114-pmc 20 - nvidia,tegra124-pmc 21 - nvidia,tegra210-pmc 22 23 reg: 24 maxItems: 1 25 description: 26 Offset and length of the register set for the device. 27 28 clock-names: 29 items: 30 - const: pclk 31 - const: clk32k_in 32 description: 33 Must includes entries pclk and clk32k_in. 34 pclk is the Tegra clock of that name and clk32k_in is 32KHz clock 35 input to Tegra. 36 37 clocks: 38 maxItems: 2 39 description: 40 Must contain an entry for each entry in clock-names. 41 See ../clocks/clocks-bindings.txt for details. 42 43 '#clock-cells': 44 const: 1 45 description: 46 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. 47 PMC also has blink control which allows 32Khz clock output to 48 Tegra blink pad. 49 Consumer of PMC clock should specify the desired clock by having 50 the clock ID in its "clocks" phandle cell with pmc clock provider. 51 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC 52 clock IDs. 53 54 '#interrupt-cells': 55 const: 2 56 description: 57 Specifies number of cells needed to encode an interrupt source. 58 The value must be 2. 59 60 interrupt-controller: true 61 62 nvidia,invert-interrupt: 63 $ref: /schemas/types.yaml#/definitions/flag 64 description: Inverts the PMU interrupt signal. 65 The PMU is an external Power Management Unit, whose interrupt output 66 signal is fed into the PMC. This signal is optionally inverted, and 67 then fed into the ARM GIC. The PMC is not involved in the detection 68 or handling of this interrupt signal, merely its inversion. 69 70 nvidia,core-power-req-active-high: 71 $ref: /schemas/types.yaml#/definitions/flag 72 description: Core power request active-high. 73 74 nvidia,sys-clock-req-active-high: 75 $ref: /schemas/types.yaml#/definitions/flag 76 description: System clock request active-high. 77 78 nvidia,combined-power-req: 79 $ref: /schemas/types.yaml#/definitions/flag 80 description: combined power request for CPU and Core. 81 82 nvidia,cpu-pwr-good-en: 83 $ref: /schemas/types.yaml#/definitions/flag 84 description: 85 CPU power good signal from external PMIC to PMC is enabled. 86 87 nvidia,suspend-mode: 88 $ref: /schemas/types.yaml#/definitions/uint32 89 enum: [0, 1, 2] 90 description: 91 The suspend mode that the platform should use. 92 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh 93 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh 94 Mode 2 is for LP2, CPU voltage off 95 96 nvidia,cpu-pwr-good-time: 97 $ref: /schemas/types.yaml#/definitions/uint32 98 description: CPU power good time in uSec. 99 100 nvidia,cpu-pwr-off-time: 101 $ref: /schemas/types.yaml#/definitions/uint32 102 description: CPU power off time in uSec. 103 104 nvidia,core-pwr-good-time: 105 $ref: /schemas/types.yaml#/definitions/uint32-array 106 description: 107 <Oscillator-stable-time Power-stable-time> 108 Core power good time in uSec. 109 110 nvidia,core-pwr-off-time: 111 $ref: /schemas/types.yaml#/definitions/uint32 112 description: Core power off time in uSec. 113 114 nvidia,lp0-vec: 115 $ref: /schemas/types.yaml#/definitions/uint32-array 116 description: 117 <start length> Starting address and length of LP0 vector. 118 The LP0 vector contains the warm boot code that is executed 119 by AVP when resuming from the LP0 state. 120 The AVP (Audio-Video Processor) is an ARM7 processor and 121 always being the first boot processor when chip is power on 122 or resume from deep sleep mode. When the system is resumed 123 from the deep sleep mode, the warm boot code will restore 124 some PLLs, clocks and then brings up CPU0 for resuming the 125 system. 126 127 i2c-thermtrip: 128 type: object 129 description: 130 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, 131 hardware-triggered thermal reset will be enabled. 132 133 properties: 134 nvidia,i2c-controller-id: 135 $ref: /schemas/types.yaml#/definitions/uint32 136 description: 137 ID of I2C controller to send poweroff command to PMU. 138 Valid values are described in section 9.2.148 139 "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference 140 Manual. 141 142 nvidia,bus-addr: 143 $ref: /schemas/types.yaml#/definitions/uint32 144 description: Bus address of the PMU on the I2C bus. 145 146 nvidia,reg-addr: 147 $ref: /schemas/types.yaml#/definitions/uint32 148 description: PMU I2C register address to issue poweroff command. 149 150 nvidia,reg-data: 151 $ref: /schemas/types.yaml#/definitions/uint32 152 description: Poweroff command to write to PMU. 153 154 nvidia,pinmux-id: 155 $ref: /schemas/types.yaml#/definitions/uint32 156 description: 157 Pinmux used by the hardware when issuing Poweroff command. 158 Defaults to 0. Valid values are described in section 12.5.2 159 "Pinmux Support" of the Tegra4 Technical Reference Manual. 160 161 required: 162 - nvidia,i2c-controller-id 163 - nvidia,bus-addr 164 - nvidia,reg-addr 165 - nvidia,reg-data 166 167 additionalProperties: false 168 169 powergates: 170 type: object 171 description: | 172 This node contains a hierarchy of power domain nodes, which should 173 match the powergates on the Tegra SoC. Each powergate node 174 represents a power-domain on the Tegra SoC that can be power-gated 175 by the Tegra PMC. 176 Hardware blocks belonging to a power domain should contain 177 "power-domains" property that is a phandle pointing to corresponding 178 powergate node. 179 The name of the powergate node should be one of the below. Note that 180 not every powergate is applicable to all Tegra devices and the following 181 list shows which powergates are applicable to which devices. 182 Please refer to Tegra TRM for mode details on the powergate nodes to 183 use for each power-gate block inside Tegra. 184 Name Description Devices Applicable 185 3d 3D Graphics Tegra20/114/124/210 186 3d0 3D Graphics 0 Tegra30 187 3d1 3D Graphics 1 Tegra30 188 aud Audio Tegra210 189 dfd Debug Tegra210 190 dis Display A Tegra114/124/210 191 disb Display B Tegra114/124/210 192 heg 2D Graphics Tegra30/114/124/210 193 iram Internal RAM Tegra124/210 194 mpe MPEG Encode All 195 nvdec NVIDIA Video Decode Engine Tegra210 196 nvjpg NVIDIA JPEG Engine Tegra210 197 pcie PCIE Tegra20/30/124/210 198 sata SATA Tegra30/124/210 199 sor Display interfaces Tegra124/210 200 ve2 Video Encode Engine 2 Tegra210 201 venc Video Encode Engine All 202 vdec Video Decode Engine Tegra20/30/114/124 203 vic Video Imaging Compositor Tegra124/210 204 xusba USB Partition A Tegra114/124/210 205 xusbb USB Partition B Tegra114/124/210 206 xusbc USB Partition C Tegra114/124/210 207 208 patternProperties: 209 "^[a-z0-9]+$": 210 type: object 211 212 patternProperties: 213 clocks: 214 minItems: 1 215 maxItems: 8 216 description: 217 Must contain an entry for each clock required by the PMC 218 for controlling a power-gate. 219 See ../clocks/clock-bindings.txt document for more details. 220 221 resets: 222 minItems: 1 223 maxItems: 8 224 description: 225 Must contain an entry for each reset required by the PMC 226 for controlling a power-gate. 227 See ../reset/reset.txt for more details. 228 229 '#power-domain-cells': 230 const: 0 231 description: Must be 0. 232 233 required: 234 - clocks 235 - resets 236 - '#power-domain-cells' 237 238 additionalProperties: false 239 240patternProperties: 241 "^[a-f0-9]+-[a-f0-9]+$": 242 type: object 243 description: 244 This is a Pad configuration node. On Tegra SOCs a pad is a set of 245 pins which are configured as a group. The pin grouping is a fixed 246 attribute of the hardware. The PMC can be used to set pad power state 247 and signaling voltage. A pad can be either in active or power down mode. 248 The support for power state and signaling voltage configuration varies 249 depending on the pad in question. 3.3V and 1.8V signaling voltages 250 are supported on pins where software controllable signaling voltage 251 switching is available. 252 253 The pad configuration state nodes are placed under the pmc node and they 254 are referred to by the pinctrl client properties. For more information 255 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. 256 The pad name should be used as the value of the pins property in pin 257 configuration nodes. 258 259 The following pads are present on Tegra124 and Tegra132 260 audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, 261 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, 262 sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. 263 264 The following pads are present on Tegra210 265 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, 266 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, 267 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, 268 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. 269 270 properties: 271 pins: 272 $ref: /schemas/types.yaml#/definitions/string 273 description: Must contain name of the pad(s) to be configured. 274 275 low-power-enable: 276 $ref: /schemas/types.yaml#/definitions/flag 277 description: Configure the pad into power down mode. 278 279 low-power-disable: 280 $ref: /schemas/types.yaml#/definitions/flag 281 description: Configure the pad into active mode. 282 283 power-source: 284 $ref: /schemas/types.yaml#/definitions/uint32 285 description: 286 Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or 287 TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. 288 The values are defined in 289 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. 290 Power state can be configured on all Tegra124 and Tegra132 291 pads. None of the Tegra124 or Tegra132 pads support signaling 292 voltage switching. 293 All of the listed Tegra210 pads except pex-cntrl support power 294 state configuration. Signaling voltage switching is supported 295 on below Tegra210 pads. 296 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, 297 sdmmc3, spi, spi-hv, and uart. 298 299 required: 300 - pins 301 302 additionalProperties: false 303 304 core-domain: 305 type: object 306 description: | 307 The vast majority of hardware blocks of Tegra SoC belong to a 308 Core power domain, which has a dedicated voltage rail that powers 309 the blocks. 310 311 properties: 312 operating-points-v2: 313 description: 314 Should contain level, voltages and opp-supported-hw property. 315 The supported-hw is a bitfield indicating SoC speedo or process 316 ID mask. 317 318 "#power-domain-cells": 319 const: 0 320 321 required: 322 - operating-points-v2 323 - "#power-domain-cells" 324 325 additionalProperties: false 326 327 core-supply: 328 description: 329 Phandle to voltage regulator connected to the SoC Core power rail. 330 331required: 332 - compatible 333 - reg 334 - clock-names 335 - clocks 336 - '#clock-cells' 337 338additionalProperties: false 339 340dependencies: 341 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] 342 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] 343 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] 344 345examples: 346 - | 347 348 #include <dt-bindings/clock/tegra210-car.h> 349 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 350 #include <dt-bindings/soc/tegra-pmc.h> 351 352 tegra_pmc: pmc@7000e400 { 353 compatible = "nvidia,tegra210-pmc"; 354 reg = <0x7000e400 0x400>; 355 core-supply = <®ulator>; 356 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 357 clock-names = "pclk", "clk32k_in"; 358 #clock-cells = <1>; 359 360 nvidia,invert-interrupt; 361 nvidia,suspend-mode = <0>; 362 nvidia,cpu-pwr-good-time = <0>; 363 nvidia,cpu-pwr-off-time = <0>; 364 nvidia,core-pwr-good-time = <4587 3876>; 365 nvidia,core-pwr-off-time = <39065>; 366 nvidia,core-power-req-active-high; 367 nvidia,sys-clock-req-active-high; 368 369 pd_core: core-domain { 370 operating-points-v2 = <&core_opp_table>; 371 #power-domain-cells = <0>; 372 }; 373 374 powergates { 375 pd_audio: aud { 376 clocks = <&tegra_car TEGRA210_CLK_APE>, 377 <&tegra_car TEGRA210_CLK_APB2APE>; 378 resets = <&tegra_car 198>; 379 power-domains = <&pd_core>; 380 #power-domain-cells = <0>; 381 }; 382 383 pd_xusbss: xusba { 384 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 385 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 386 power-domains = <&pd_core>; 387 #power-domain-cells = <0>; 388 }; 389 }; 390 }; 391